noc_fw_ddr_l3_ddr_scr Address Map

Module Instance Base Address End Address
noc_fw_ddr_l3_ddr_scr 0xFFD13400 0xFFD134FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
enable 0x0 32 RW 0x0 
Enable
enable_set 0x4 32 WO 0x0 
Sets Master Region Enable field when written with 1
enable_clear 0x8 32 WO 0x0 
Clears Master Region Enable field when written with 1
hpsregion0addr 0xC 32 RW 0x0 
Base and Limit definition for HPS Region 0
hpsregion1addr 0x10 32 RW 0x0 
Base and Limit definition for HPS Region 1
hpsregion2addr 0x14 32 RW 0x0 
Base and Limit definition for HPS Region 2
hpsregion3addr 0x18 32 RW 0x0 
Base and Limit definition for HPS Region 3
hpsregion4addr 0x1C 32 RW 0x0 
Base and Limit definition for HPS Region 4
hpsregion5addr 0x20 32 RW 0x0 
Base and Limit definition for HPS Region 5
hpsregion6addr 0x24 32 RW 0x0 
Base and Limit definition for HPS Region 6
hpsregion7addr 0x28 32 RW 0x0 
Base and Limit definition for HPS Region 7
global 0x2C 32 RW 0x0 
Global Firewall Control Register. This register will store various overrides that change default firewall behavior on the entire interconnect.