global

         Global Firewall Control Register. This register will store various overrides that change default firewall behavior on the entire interconnect.

Module Instance	Base Address	Register Address
`noc_fw_ddr_l3_ddr_scr`	`0xFFD13400`	`0xFFD1342C`

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`error_response` `RW 0x0`

global Fields

Bit	Name	Description	Access	Reset
0	`error_response`	When 0, transactions blocked by the firewall will fail silently, returning random data and no error status. When 1, transactions blocked by the firewall will return an error. Note: Future devices might not support the return of random data and might only support an error response for blocked firewall transactions. For designs that might be ported to future devices, Intel recommends you to set the error_response bit.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

error_response

When 0, transactions blocked by the firewall will fail silently, returning random data and no error status.  When 1, transactions  blocked by the firewall will return an error.

Note: Future devices might not support the return of random data and might only support an error response for blocked firewall transactions. For designs that might be ported to future devices, Intel recommends you to set the error_response bit.

RW

0x0