noc_mpu_m0_ddr_T_main_Scheduler Address Map

Module Instance	Base Address	End Address
`i_noc_mpu_m0_ddr_T_main_Scheduler`	`0xFFD12400`	`0xFFD12FFF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`ddr_T_main_Scheduler_Id_CoreId`	`0x0`	`32`	`RO`	`0x7242E202`
`ddr_T_main_Scheduler_Id_RevisionId`	`0x4`	`32`	`RO`	`0x129FF00`
`ddr_T_main_Scheduler_DdrConf`	`0x8`	`32`	`RW`	`0x0`	ddr configuration definition.
`ddr_T_main_Scheduler_DdrTiming`	`0xC`	`32`	`RW`	`0xAC2A14DC`	ddr timing definition.
`ddr_T_main_Scheduler_DdrMode`	`0x10`	`32`	`RW`	`0x0`	ddr mode definition.
`ddr_T_main_Scheduler_ReadLatency`	`0x14`	`32`	`RW`	`0x13`
`ddr_T_main_Scheduler_Activate`	`0x38`	`32`	`RW`	`0x4D2`	timing values concerning Activate commands, in Generic clock unit.
`ddr_T_main_Scheduler_DevToDev`	`0x3C`	`32`	`RW`	`0x15`	timing values concerning device to device data bus ownership change, in Generic clock unit.