ddr_T_main_Scheduler_DdrConf

         ddr configuration definition.
Module Instance Base Address Register Address
i_noc_mpu_m0_ddr_T_main_Scheduler 0xFFD12400 0xFFD12408

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

DDRCONF

RW 0x0

ddr_T_main_Scheduler_DdrConf Fields

Bit Name Description Access Reset
4:0 DDRCONF 
Selection of a configuration of mappings of address bits to memory device, bank, row, and
column. 
0x00: R12_B3_C10: All types

0x01: R13_B3_C10: All types

0x02: R14_B3_C10: All types

0x03: R15_B3_C10: All types

0x04: R16_B3_C10: All types

0x05: R17_B3_C10: All types

0x06: R14_B3_C11: Reserved

0x07: R15_B3_C11: Reserved 

0x08: R16_B3_C11: DDR3 8Gb

0x09: R15_B3_C12: Reserved
 
0x0A: R14_B4_C10: DDR4 only

0x0B: R15_B4_C10: DDR4 only

0x0C: R16_B4_C10: DDR4 only

0x0D: R17_B4_C10: DDR4 only

0x0E: B3_R12_C10: Min DDR3 512Mbit x16

0x0F: B3_R13_C10: DDR3 512Mb x8 or 1Gb x16

0x10: B3_R14_C10: Min DDR4 1Gb x8 or DDR3 1Gb x8 or 2Gb x16

0x11: B3_R15_C10: DDR3 2Gb x8 & 4Gb x16 or LPDDR3 8Gb x32

0x12: B3_R16_C10: DDR3 4Gb x8 & 8Gb x16

0x13: B3_R17_C10: DDR4 16Gb x16

0x14: B3_R14_C11: Reserved

0x15: B3_R15_C11: Reserved
  
0x16: B3_R16_C11: DDR3 8Gb x8

0x17: B3_R15_C12: Reserved
 
0x18 B4_R14_C10: DDR4 2Gb x8

0x19 B4_R15_C10: DDR4 4Gb x8

0x1A B4_R16_C10: DDR4 8Gb x8

0x1B B4_R17_C10: DDR4 16Gb x8
 RW 0x0