noc_mpu_m0_ddr_T_main_Scheduler Summary

Base Address: 0xFFD12400

Register Address Offset	Bit Fields
`i_noc_mpu_m0_ddr_T_main_Scheduler`
`ddr_T_main_Scheduler_Id_CoreId` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CORECHECKSUM` `RO 0x7242E2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CORECHECKSUM` `RO 0x7242E2`								`CORETYPEID` `RO 0x2`
`ddr_T_main_Scheduler_Id_RevisionId` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FLEXNOCID` `RO 0x129FF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FLEXNOCID` `RO 0x129FF`								`USERID` `RO 0x0`
`ddr_T_main_Scheduler_DdrConf` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`DDRCONF` `RW 0x0`
`ddr_T_main_Scheduler_DdrTiming` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BWRATIO` `RW 0x1`	`WRTORD` `RW 0xB`					`RDTOWR` `RW 0x1`					`BURSTLEN` `RW 0x2`			`WRTOMISS` `RW 0x21`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WRTOMISS` `RW 0x21`				`RDTOMISS` `RW 0x13`						`ACTTOACT` `RW 0x1C`
`ddr_T_main_Scheduler_DdrMode` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`BWRATIOEXTENDED` `RW 0x0`	`AUTOPRECHARGE` `RW 0x0`
`ddr_T_main_Scheduler_ReadLatency` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`READLATENCY` `RW 0x13`
`ddr_T_main_Scheduler_Activate` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`					`FAWBANK` `RW 0x1`	`FAW` `RW 0xD`						`RRD` `RW 0x2`
`ddr_T_main_Scheduler_DevToDev` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`BUSWRTORD` `RW 0x1`		`BUSRDTOWR` `RW 0x1`		`BUSRDTORD` `RW 0x1`