timer Address Map

Module Instance	Base Address	End Address
`i_timer_sp_0_timer`	`0xFFC02700`	`0xFFC027FF`
`i_timer_sp_1_timer`	`0xFFC02800`	`0xFFC028FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`timer1loadcount`	`0x0`	`32`	`RW`	`0x0`	Name: Timer1 Load Count Register Size: 8-32 bits Address Offset: 0x00 Read/Write Access: Read/Write
`timer1currentval`	`0x4`	`32`	`RO`	`0x0`	Name: Timer1 Current Value Size: 8-32 bits Address Offset: 4 Read/Write Access: Read
`timer1controlreg`	`0x8`	`32`	`RW`	`0x0`	Name: Timer1 Control Register Size: 3 bits Address Offset: 8 Read/Write Access: Read/Write This register controls enabling, operating mode (free-running or defined-count), and interrupt mask of Timer1. You can program each Timer1ControlReg to enable or disable a specific timer and to control its mode of operation.
`timer1eoi`	`0xC`	`32`	`RO`	`0x0`	Name: Timer1 End-of-Interrupt Register Size: 1 bit Address Offset: 12 Read/Write Access: Read
`timer1intstat`	`0x10`	`32`	`RO`	`0x0`	Name: Timer1 Interrupt Status Register Size: 1 bit Address Offset: 16 Read/Write Access: Read
`timersintstat`	`0xA0`	`32`	`RO`	`0x0`	Name: Timers Interrupt Status Register Size: 1-9 bits Address Offset: 0xa0 Read/Write Access: Read
`timerseoi`	`0xA4`	`32`	`RO`	`0x0`	Name: Timers End-of-Interrupt Register Size: 1-9 bits Address Offset: 0xa4 Read/Write Access: Read
`timersrawintstat`	`0xA8`	`32`	`RO`	`0x0`	Name: Timers Raw Interrupt Status Register Size: 1-9 bits Address Offset: 0xa8 Read/Write Access: Read
`timerscompversion`	`0xAC`	`32`	`RO`	`0x3230382A`	Name: Timers Component Version Size: 32 bits Address Offset: 0xac Read/Write Access: Read