timer1controlreg
Name: Timer1 Control Register
Size: 3 bits
Address Offset: 8
Read/Write Access: Read/Write
This register controls enabling, operating mode (free-running or defined-count), and interrupt mask of
Timer1. You can program each Timer1ControlReg to enable or disable a specific timer and to control
its mode of operation.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_timer_sp_0_timer | 0xFFC02700 | 0xFFC02708 |
| i_timer_sp_1_timer | 0xFFC02800 | 0xFFC02808 |
Offset: 0x8
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
timer1_interrupt_mask RW 0x0 |
timer1_mode RW 0x0 |
timer1_enable RW 0x0 |
||||||||||||
timer1controlreg Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 2 | timer1_interrupt_mask | Timer interrupt mask for Timer1. 0: not masked 1: masked
|
RW | 0x0 | ||||||
| 1 | timer1_mode | Timer mode for Timer1. 0: free-running mode 1: user-defined count mode NOTE: You must set the Timer1LoadCount register to all 1s before enabling the timer in free-running mode.
|
RW | 0x0 | ||||||
| 0 | timer1_enable | Timer enable bit for Timer1. 0: disable 1: enable
|
RW | 0x0 |