FPGA Address Map

Module Instance Base Address End Address
CCU_fpga10 0xF7001000 0xF7001FFF
Register Offset Width Access Reset Value Description
CAIUTCR 0x0 32 RW 0x00000001 
CAIU Transaction Control Register
CAIUTAR 0x4 32 RO 0x00000000 
CAIU Transaction Activity Register
CAIUTTR 0x8 32 RW 0x00000000 
CAIU Transaction Throttle Register
CAIUCECR 0x100 32 RW 0x00000000 
CAIU Correctable Error Control Register
CAIUCESR 0x104 32 RW 0x00000000 
CAIU Correctable Error Status Register
CAIUCELR0 0x108 32 RW 0x00000000 
CAIU Correctable Error Location Register 0
CAIUCELR1 0x10C 32 RW 0x00000000 
CAIU Correctable Error Location Register 1
CAIUCESAR 0x124 32 RW 0x00000000 
CAIU Correctable Error Status Alias Register
CAIUUECR 0x140 32 RW 0x00000000 
CAIU Uncorrectable Error Control Register
CAIUUESR 0x144 32 RW 0x00000000 
CAIU Uncorrectable Error Status Register
CAIUUELR0 0x148 32 RW 0x00000000 
CAIU Uncorrectable Error Location Register 0
CAIUUELR1 0x14C 32 RW 0x00000000 
CAIU Uncorrectable Error Location Register 1
CAIUUESAR 0x164 32 RW 0x00000000 
CAIU Uncorrectable Error Status Alias Register
CAIUDCR 0xF00 32 RW 0x00000000 
CAIU Debug Control Register
CAIUDAR 0xF04 32 RO 0x00000000 
CAIU Debug Activity Register
CAIUDLR 0xF08 32 RW 0x00000000 
CAIU Debug Location Register
CAIUDDR 0xF10 32 RO 0x00000000 
CAIU Debug Data Register
CAIUIDR 0xFFC 32 RO 0x00030101 
CAIU Identification Register