FPGA Summary

Base Address: 0xF7001000

Register Address Offset	Bit Fields
`CCU_fpga10`
`CAIUTCR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`														`IsolEn` `RW 0x0`	`TransEn` `RW 0x1`
`CAIUTAR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`													`CohActv` `RO 0x0`	`SnpActv` `RO 0x0`	`TransActv` `RO 0x0`
`CAIUTTR` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TransThrottleEn` `RW 0x0`	`TransThrottleMask` `RW 0x0`	`rsvd2` `RO 0x0`						`TransDelta` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`								`TransLimit` `RW 0x0`
`CAIUCECR` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd2` `RO 0x0`				`ErrThreshold` `RW 0x0`								`rsvd1` `RO 0x0`		`ErrIntEn` `RW 0x0`	`ErrDetEn` `RW 0x0`
`CAIUCESR` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd2` `RO 0x0`								`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RO 0x0`				`ErrCount` `RO 0x0`								`rsvd1` `RO 0x0`		`ErrOvf` `RW 0x0`	`ErrVld` `RW 0x0`
`CAIUCELR0` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`CAIUCELR1` `0x10C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`				`ErrAddr` `RW 0x0`
`CAIUCESAR` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd2` `RO 0x0`								`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RW 0x0`				`ErrCount` `RW 0x0`								`rsvd1` `RO 0x0`		`ErrOvf` `RW 0x0`	`ErrVld` `RW 0x0`
`CAIUUECR` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd2` `RO 0x0`				`ErrThreshold` `RO 0x0`								`rsvd1` `RO 0x0`		`ErrIntEn` `RW 0x0`	`ErrDetEn` `RW 0x0`
`CAIUUESR` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd2` `RO 0x0`								`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RO 0x0`				`ErrCount` `RO 0x0`								`rsvd1` `RO 0x0`		`ErrOvf` `RW 0x0`	`ErrVld` `RW 0x0`
`CAIUUELR0` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`CAIUUELR1` `0x14C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`				`ErrAddr` `RW 0x0`
`CAIUUESAR` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd2` `RO 0x0`								`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrType` `RW 0x0`				`ErrCount` `RW 0x0`								`rsvd1` `RO 0x0`		`ErrOvf` `RW 0x0`	`ErrVld` `RW 0x0`
`CAIUDCR` `0xF00` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`												`DbgOp` `RW 0x0`
`CAIUDAR` `0xF04` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd1` `RO 0x0`														`DbgOpFail` `RO 0x0`	`DbgOpActv` `RO 0x0`
`CAIUDLR` `0xF08` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DbgWord` `RW 0x0`						`DbgStruct` `RW 0x0`						`DbgEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DbgEntry` `RW 0x0`
`CAIUDDR` `0xF10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DbgData` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DbgData` `RO 0x0`
`CAIUIDR` `0xFFC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd1` `RO 0x0`							`SfId` `RO 0x0`					`Type` `RO 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Ca` `RO 0x0`	`CaiId` `RO 0x1`							`ImplVer` `RO 0x1`