Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 GX FPGA contains up to 10.2 million LEs and features 96 general-purpose transceivers on separate chiplets. With 2666 Mbps DDR4 external memory interface performance, these devices are optimized for FPGA applications requiring the highest transceiver, IO bandwidth, and core fabric performance.
Intel® Stratix® 10 GX FPGA
Meet High-Performance Demands
Benefits
High Clock Performance and Lower Power Consumption
Intel® Stratix® 10 FPGAs and SoC FPGAs use the Intel® Hyperflex™ core architecture, delivering higher throughput, improved power efficiency, greater design functionality, and increased designer productivity compared to previous generations.
First Intel® FPGA to Run on the Hyperflex™ FPGA Architecture
The Intel® Hyperflex™ FPGA Architecture introduces bypassable Hyper-Registers throughout the FPGA fabric on every interconnect routing segment and at the inputs of all functional blocks. Hyper-registers enable three key design techniques to achieve core performance increases: Hyper-Retiming to eliminate critical paths, Hyper-Pipelining to eliminate routing delays, and Hyper-Optimization to achieve the best performance.
Enabling Next-Generation Chiplets Using Intel’s 3D System-in-Package Technology
The patented Embedded Multi-Die Interconnect Bridge (EMIB) technology provides a simple integration flow and offers an ultra-high density interconnect between heterogeneous dies in the same package. It also enables in-package functionality that was either too complex or too cost-prohibitive to implement with alternative in-package integration solutions.
Applications
Wireline and Wireless Communication Infrastructure
With the introduction of the Intel® HyperFlex™ FPGA Architecture, fMAX over 700MHz is achieved, enabling high-speed networking standards like 400GB Ethernet. These features empower our FPGAs to efficiently handle complex tasks, bridging protocols, aggregating data, and optimizing wireline and wireless communication infrastructure at a fraction of the power.
Military Radar and Secure Communication System
This FPGA excels in rapid signal processing and encryption, with up to 10 TFLOPS of IEEE 754-compliant single-precision floating-point performance and core frequencies of up to 1 GHz. Its beam former IP ensures high-throughput beam processing for precise radar beam steering. It features Secure Device Manager (SDM) with security services like Sector-based authentication, Multi-factor authentication, Physically Unclonable Function (PUF), and enhanced resilience to single-event upsets (SEUs), supporting fault-tolerant designs for uninterrupted operation during hardware failures or attacks.
Application Specific Integrated Circuits (ASIC) Prototyping
The Intel® Stratix® 10 GX FPGA, with up to 10.2 million LEs, streamlines ASIC prototyping. Its monolithic FPGA fabric increases productivity by lowering design partitioning complexity, while maximum I/O counts and integrated IP for writeback and readback enhance flexibility and debug productivity. This allows designers to refine their ASIC designs before committing to costly fabrication.
Key Features
Intel® Hyperflex™ FPGA Architecture
The core architecture delivers many advantages: higher throughput, improved power efficiency, greater design functionality, increased designer productivity and incorporates bypassable hyper-registers.
Heterogeneous 3D SiP Transceiver Tiles
The transceivers are on the heterogeneous 3D System-in-Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels offering solutions for connectivity needs and future flexibility and scalability needs as data rates, modulation schemes, and protocol IPs evolve.
Secure Device Manager (SDM)
SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks.
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