F-Tile PCIe Hard IP
The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes. F-Tile serves as a companion tile for Agilex™ 7 devices.
F-Tile is the successor of P-Tile and natively supports PCIe 3.0 and 4.0 configurations.
Read the F-Tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›
Read the F-Tile Avalon® Streaming Intel® FPGA IP for PCIe design example user guide ›
F-Tile PCIe Hard IP
Standards & Specifications Compliance
- PCIe Base Specification Revision 4.0
- Single Root I/O Virtualization and Sharing Specification, Rev 1.1
- Address Translation Services, Revision 1.1
- PHY Interface for PCIe Architectures, Version 4.0
- Virtual I/O Device (VIRTIO) Version 1.0
Features
- Includes a complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as Hard IP
- PIPE mode support
- Natively supports PCIe* 4.0/3.0 configurations with support for 2.0/1.0 configurations support via link down-training
- Supports Root Port and Endpoint modes
- Support for TL-Bypass mode to enable either Up-port or Down-port functionality for working with fabric-based PCIe Switch IP
- Various multilink EP, RP modes in lower width x4, x8 configurations available
- Up to 512-byte Maximum Payload Size (MPS)
- Up to 4096-byte (4 KB) Maximum Read Request Size (MRRS)
- Single Virtual Channel (VC) Support
- Supports Completion Timeout Ranges through Completion Timeout Interface
- Atomic Operations (FetchAdd/Swap/CAS)
- Support for various clocking modes: Common Reference Clock (refclk), Independent Reference Clock (refclk) with and without Spread spectrum (SRIS, SRNS)
- Advanced Error Reporting
- Precision Time Management (PTM)
- ECRC generation and checking
- Supports D0 and D3 PCIe power states
- Lane margining at receiver
- Retimers presence detection
- Supports autonomous Hard IP mode that allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete
- FPGA core Configuration via PCIe link (CVP Init and CVP Update) and Partial Reconfiguration (PR) over PCIe link
Multifunction and Virtualization Features
- SR-IOV support (8 PFs, 2K VFs per each Endpoint)
- VirtIO support via configuration intercept interface
- Scalable I/O and Shared Virtual Memory (SVM) support
- Access Control Service (ACS)
- Alternative Routing-ID Interpretation (ARI)
- Function Level Reset (FLR)
- Support for TLP Processing Hint (TPH)
- Address Translation Services (ATS)
- Process Address Space ID (PasID)
User Interface Features
- Avalon® Streaming Interface (Avalon-ST)
- User packet interface with separate header, data, and prefix
- Dual segmented user packet interface with the ability to handle up to two TLPs in any given cycle (x16 core only)
- Extended Tag Support
- 10-bit Tag Support (maximum of 768 outstanding tags (x16) / 512 outstanding tags (x4/x8) at any given time, for all functions combined)
IP Debug Features
- Debug toolkit features:
- Protocol and link status information
- Basic and advanced debugging capabilities including PMA register access and Eye Viewing capability
Driver Support
- Ubuntu device drivers
Related Links
Documentation
Device and Hardware Development Kit Support
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