eCPRI Altera® FPGA IP

The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0. It is a front-haul interface protocol for radio base stations aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.

Read the eCPRI Altera® FPGA IP user guide ›

Read the eCPRI Altera® FPGA IP design example user guide ›

eCPRI Altera® FPGA IP

Features

  • Compliant with the eCPRI Specification V2.0 (2018-06-25) available on the CPRI Industry Initiative (CII) website.
  • Supports eCPRI radio equipment controller (eREC) and eCPRI radio equipment (eRE) module configurations.
  • Supports Ethernet headers in a variety of formats, including VLAN tag, source/destination MAC address, IPv4, UDP extraction and encapsulation.
  • Supports eCPRI one-way delay measurement based on IEEE Standard 1588 Precision Time Protocol (1588 PTP) hardware timestamp. Full hardware support, and required 1588 PTP software stack.
  • Supports 25 Gbps and 10 Gbps Ethernet ports.
  • Supports pairing of eCPRI Altera® FPGA IP with O-RAN Altera® FPGA IP.

IP Status

 

Ordering Status

Production

Ordering Code

IP-eCPR
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