Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration. This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.
Read the 1G/2.5G/5G/10G Multirate Ethernet PHY Agilex™ 5 FPGA IP user guide ›
Read the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Stratix® 10 FPGA IP user guide ›
Read the Arria® 10 Transceiver PHY user guide ›
Read the Cyclone® 10 GX Transceiver PHY user guide ›
Read the V-Series Transceiver PHY IP core user guide ›
Read the F-Tile Ethernet Multirate Intel® FPGA IP user guide ›
Read the F-Tile CPRI PHY Multirate Intel® FPGA IP user guide ›
Read the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP release notes ›
Read the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP user guide ›
Read the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP user guide ›
Multi-Rate Ethernet PHY FPGA IP
The 2.5G and 5G Ethernet configurations were introduced to support higher bandwidth on widely deployed CAT5e and CAT6 cabling in enterprise and metro area networks.
Check out the following Chalk Talk video to learn more about the FPGA 2.5G Ethernet solution ›
Features
- Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard.
- Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA).
- Dynamically switchable PHY operating speed.
- 1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M, 100M, 1G, 2.5G, 10G (MGBASE-T) operating modes.
- Users needing Copper-PHY capability for USXGMII, MGBASE-T modes will need to use an external PHY chip.
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