Agilex™ 7 FPGA and SoC FPGA M-Series
M-Series devices are optimized for compute- and memory-intensive applications. Leveraging Intel 7 process technology, this series builds upon I-Series device features offering an extensive memory hierarchy including integrated high-bandwidth memory (HBM) with digital signal processing (DSP) and high-efficiency interfaces to DDR5 memory with a hard memory Network-on-Chip (NoC) to maximize memory bandwidth.
Agilex™ 7 FPGA and SoC FPGA M-Series
Highest Memory Bandwidth1
Up to
1TBps
as the industry’s highest memory bandwidth FPGA1
The industry’s highest
DSP
compute density in an HBM-enabled FPGA2
The industry’s 1st
DDR5
enabled high-end FPGA
Up to
1TBps
as the industry’s highest memory bandwidth FPGA1
The industry’s highest
DSP
compute density in an HBM-enabled FPGA2
The industry’s 1st
DDR5
enabled high-end FPGA
Massive Memory Bandwidth FPGA
The M-Series FPGA, with in-package HBM2E memory, support for LPDDR5, DDR5, and DDR4 memory, features a new hardened memory network-on-chip (NoC) to enable massive memory bandwidth with improved efficiency and fewer FPGA resources required.
The Go-To Solution for Massive Memory Bandwidth
Watch how M-Series FPGAs provide a solution to your most challenging memory bandwidth applications.
Benefits
Built for Fast and High Bandwidth Memory Applications
The M-Series FPGA wide and flexible memory hierarchy with dual dedicated hardened memory controllers, and hardened memory Network on Chip (NoC) allows designers to reach the highest HBM2E and DDR5 memory bandwidth and run the memory computation near the fabric, significantly reducing memory bottlenecks and latency.
High Compute Capability
Do the work of multiple FPGAs in one. Up to 37 TFLOPs of FP16 performance3, up to 116 Gbps transceiver rates, and up to 3.9M logical elements (LE) deliver extreme density in an FPGA.
Support for High-Bandwidth and Coherent Attach to Intel Processors
Directly attach M-Series FPGA to Intel® Xeon® Scalable processors over the PCIe 5.0 bus or use the new Compute Express Link (CXL) protocol for exceptional I/O performance in moving compute workloads between CPU and FPGA.
Use Cases and Applications
Overcome Memory Bottlenecks
M-Series FPGAs combine high fabric densities and flexible memory options such as HBM2E, LPDDR5, DDR5, and DDR4 memory support to provide the right balance of capacity, power efficiency, and performance for memory-driven workloads in Network, Broadcast, Cloud, and more.
Enable Next-Gen Applications with a Data Superhighway
Offering the industry’s highest speed transceivers (116G PAM4), PCIe 5.0, Compute Express Link, 400G Ethernet, and the highest DSP compute density2, the M-Series devices can support the throughput requirements of the most demanding applications from the data center to the edge.
Key Features
Variable-precision DSP
Up to 38 TFLOPs of FP16 performance3, up to 116 Gbps transceiver rates, and up to 3.9M logical elements (LE) deliver extreme density in an FPGA.
Hardened Memory Network-on-Chip
By using Hardened memory NoC, unleash the industry’s highest memory bandwidth, up to 1TBps, using in-package HBM2E (up to 32GB capacity) and hardened DDR5/LPDDR5 memory controller (supporting 5,600 Mbps).
Second Generation Intel® Hyperflex™ FPGA Architecture
This core fabric offers key advantages to enable significant design optimization and key advantages to deliver higher performance, lower total power, greater design functionality, and increased designer productivity.
Configurable 116Gb/s Transceivers
M-series includes industry’s fastest transceivers 58G/116Gb/s PAM4 and 32GB/s NRZ to allow deployment of 800G Ethernet and single-lane 100Gb/s.
PCIe 5.0
PCI Express (PCIe) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 giga transfers per second (GT/s) to 32.0 GT/s.
Compute Express Link (CXL)
CXL enables M-series to attach to Intel® Xeon® Scalable processor offering exceptional I/O performance in moving compute workloads between CPU and FPGA.
Related Links
Additional Resources
Explore more content related to Altera® FPGA devices such as development boards, intellectual property, support and more.
Support Resources
Resource center for training, documentation, downloads, tools and support options.
Development Boards
Get started with our FPGA and accelerate your time-to-market with Altera-validated hardware and designs.
Intellectual Property
Shorten your design cycle with a broad portfolio of Altera-validated IP cores and reference designs.
FPGA Design Software
Explore Quartus Prime Software and our suite of productivity-enhancing tools to help you rapidly complete your hardware and software designs.
Contact Sales
Get in touch with sales for your Altera® FPGA product design and acceleration needs.
Where to Buy
Contact an Altera® Authorized Distributor today.
Product and Performance Information
Agilex™ 7 FPGA M-Series theoretical maximum bandwidth of 1.099 TBps with 2 banks of HBM2e using ECC as data and 8 DDR5 DIMMs as compared to Xilinx Versal HBM memory bandwidth of 1.056 TBps as of October 14, 2021, and to Achronix Speedster 7t memory bandwidth of 0.5 TBps as of October 14, 2021.
Agilex™ 7 FPGA M-Series DSP compute density projected at 88.6 INT8 TOPs and 18.45 FP32 TFLOPs, compared to Xilinx Versal HBM at 74.9 INT8 TOPs and 17.5 FP32 TFLOPs of October 14, 2021, and to Achronix Speedster 7t at 61.4 INT8 TFLOPs and no support for FP32, as of October 14, 2021.
Each Agilex™ FPGA DSP block can perform two FP16 floating-point operations (FLOPs) per clock cycle. Total FLOPs for FP16 configuration is derived by multiplying 2x the maximum number of DSP blocks to be offered in a single Agilex™ FPGA by the maximum clock frequency that will be specified for that block.