Gidel was founded in 1993 and has been continuously providing Intel® FPGA-based hardware and software products to the marketplace. Gidel products are optimized for diverse markets such as HPC, Imaging-Vision, and ATEs. Gidel's COTS hardware are robust, reliable and have long life-cycle with quality ISO 9001-2008. It offers customization to meet end user's system requirement and these systems are used by large OEMs in production. Gidel specializes in high-performance grabbing and real-time processing continuously providing best-in-market imaging and vision performance.
Offerings
Offering
Industry's first FPGA module and PCIe board based on the novel Intel® Stratix 10 NX. These compact solutions enable complex AI and other compute-intensive applications requiring high data rate and low-latency. The Stratix 10 NX incorporates newly developed Tensor blocks for fast AI and vector processing. The Tensor blocks integrated with HBM2 memory offers an unprecedented level of computation performance and memory bandwidth. Key Features Stratix 10NX 2100 FPGA: 143 / 286 INT8 / INT4 TOPS or 143 / 286 Block FP16 / FP12 TFLOPS ideal for AI and array processing Ultra-high bandwidth 8 GB HBM2 2,073,000 LEs Ultra-compact module (97.4mm x 101mm / 3.83” x 3.98”) Flexible usage via customized carrier board or via Gidel’s carrier board 5-level memory scheme (50 TB/s+): 50 TB/s access to MLABs 41 TB/s access to M20Ks • 90 GB/s access to SRAMs 400 GB/s access to DRAMs Max capacity>512 GB 8 GB on module 512 GB (Optane) or 128 GB (RDIMM) on carrier 72 Transceivers with bandwidth>1,600 Gb/s (TX+RX): 48 x up to 26 Gb/s PCIe Gen3 x16 8 x up to 16 Gb/s 374 I/Os PLLs with jitter cleaners (100fs) 10 dedicated input reference clocks 2 x output reference clock Max power utilization: 120W (@12V) Active or passive cooling and heating May be used on half-length PCIe carrier board
Offering
The Proc10A™ system is a flexible, high-performance, low-power, Multi 10GigEVision FPGA Grabbing platform based on Altera’s powerful Arria 10 FPGA. The Proc10A’s unique architecture balances high performance and flexibility to meet demanding and versatile Grabbing and Image Processing requirements. With up to fifteen 14.2 Gb/s full-duplex transceivers and vast memory resources, the Proc10A offers tremendous I/O throughput along with powerful on-board processing and data management capabilities ideal for high-end imaging applications. A multi-level memory scheme includes up to 32 GB DDR3 ECC SODIMM, on-board 1 GB DDR3 SDRAM, dedicated FPGA memory blocks (M20K and MLABs), and other memory options. In addition, the Proc10A hosts an 8-lane PCI Express Gen. 3 bridge that enables strong co-processing between the host CPU and the FPGA accelerator. For tightly-coupled FPA and CPU processing, Gidel offers the Proc10A SoC family, with an embedded ARM processor based on the Arria 10 SoC FPGAs. The Proc10A is supported by Gidel ProcVision Tool Kit, HLS, and Gidel’s innovative development tools, and enables high productivity based on C and HDL designs.
Offering
The HawkEye is a low-profile PCIe accelerator based on Intel’s Arria 10 FPGAs . The platform boasts up to 18 GB DDR4 on-board memory, 2 SFP+ links for a maximum of 28 Gb/s, and a PCIe x8 Gen. 3 host interface. The Arria 10 FPGA provides up to 480K LEs and IEEE floating-point capability. The HawkEye’s memory scheme is composed of embedded SRAM memory, 1-2 GB DDR4, and up to 16 GB of DDR4 SoDIMM (only for boards with 480 devices). The DDR memory may be accessed via up to 48 parallel ports simultaneously.The HawkEye family includes an option for SoC Hard Processor System (HPS) based on Arria 10 SX devices with an embedded dual core ARM processor. The SoC boards are supported by a MicroSD memory card allowing storage of large program images for stand-alone mode.The HawkEye accelerator board exhibits an impressive power efficiency, starting at less than 12W. The board is fortified by abundant I/O interface possibilities, including RS422, Opto-coupler, external clock, LVDS, LVTTL (3V), and 30V/0.9A output. The HawkEye can operate as a PCIe-based platform or as a stand-alone compute accelerator. The system has been designed for exceptional high reliability with an MTBF beyond 1 million hours.The HawkEye is supported by Gidel’s unique proprietary tools for developing on FPGA. These tools offer a solution that is unique in the market and can be used together with Intel’s design tools to achieve unmatched development efficiency and efficacy. The Gidel development tools suite includes Gidel’s Developer’s kit as well as Gidel HLS (i++) ASP based on Intel’s SDK.
Offering
The Gidel HawkEye-CXP-12 CoaXPress frame grabbing and real-time image processing system provides the core infrastructure required to realize the most demanding vision and imaging applications. The HawkEye series offers a number of options to accommodate diverse application needs, from plug-and-play high-performance frame grabbers to a full system solution comprising acquisition, open-FPGA image processing, and flexible custom camera interface. The HawkEye-CXP is CoaXPress supports up to four CoaXPress (cXp-12/ cXp-6) links enabling connecting 1 - 4 CXP-12 cameras. The HawkEye-CXP family is based on PCIe Gen. 3 x8, providing CPU-free ultra-fast offload bandwidth. Large data buffers of up to 16 GB fortify the acquisition bandwidth and the image processing capabilities on powerful Arria 10 FPGA. The board is supported by the Gidel ProcVision Kit allowing users to tailor their Vision flows in an intuitive and simple manner by customizing both the software and the FPGA design code for different frame grabbing flavors.
Offering
The Proc10A_CXP-12 grabber and image processing family offers a number of options to accommodate diverse application needs, from plug-and-play high-performance frame grabbers to a full custom system solution comprising user-tailored acquisition path, on-FPGA image processing, real-time compression and more. The Proc10A_CXP-12 is designed for ultra-high bandwidth combining 8x CXP-12/6 links for up to 10 GB/s, PCIe Gen. 3 x8 host interface, huge image buffers of up to 32 GB, real-time compression and ability to offload Regions Of Interest (ROI) for additional bandwidth utilization. The Proc10A_CXP-12 enables the use of eight 500+ MPixels/s Gidel Lossless and JPEG encoders - twice the pixel frequency of any other available solution. The Proc10A_CXP-12, based on Intel® Arria® 10 FPGAs, delivers tremendous processing capacity fortified with abundant memory resources enabling to implement real-time image processing and user algorithms.
Offering
The Gidel HawkEye-20GigE frame grabbing and real-time image processing system offers true 10 GigE acquisition capabilities guaranteeing 100%frame capture with no frame loss. The board is supported by comprehensive system I/Os, ROI capture capability, multi-link aggregation and chunk data (payload type: 0x4001) transmission. The HawkEye-20GigE series offers a number of options to accommodate diverse application needs, from a plug-and-play high-performance frame grabber to a fully customized system solution comprising acquisition, FPGA image processing, real-time image compression, multi-camera synchronization and complex I/O system control. The HawkEye-20GigE has an acquisition bandwidth of 20 Gb/s via two SFP+ ports enabling grabbing from two 10 GigE cameras, multi-link cameras or multiple GigE cameras via a switch. The HawkEye-10GigE family is based on PCIe Gen. 3 x8, providing CPU-free ultra-fast offload bandwidth. The boards are supported by Gidel’s development tools, including the ProcVision Kit for tailoring, debugging and verifying the FPGA image processing and data flow, and the Proc Dev Kit for generating automatically the Application Support Packages (ASPs) and the environment FPGA code, including all board/IP constrains and user logic wrapper.
Offering
The Gidel CamSim™ is a flexible high-performance camera simulator that generates a camera link video stream and test patterns for testing frame grabbers or vision/imaging systems. The system supports all Camera Link™ specification v2.0 configurations and can be customized for any user-defined camera protocol and interface. The CamSim enables most development to be done in a low-cost lab environment. Thus, the CamSim significantly improves productivity and reduces the overall expense of developing vision and imaging systems. Gidel’s CamSim data flow repetition capability ensures that algorithms are validated and work as expected with pertinent input. Moreover, once the rare bug is detected, its respective data flow can be accurately reconstructed to locate the bug and quickly fix it. The CamSim suite includes: Application Software: An intuitive GUI enabling full control of the image simulation, including: transmitting image from user files or pattern generator files and configuring the camera link and timing parameters. API Methods: A set of CamSim API methods that can be used to develop a customized user application. Gidel PCIe Board: A PCIe FPGA board incorporating Gidel CamSim firmware for transmitting the image data.
Offering
The Gidel HawkEye-CL frame grabbing and real-time image processing system provides the core infrastructure required to support the most demanding vision and imaging applications. The HawkEye series offers a number of options to accommodate diverse application needs, from plug-and-play high- performance frame grabbers to a full system solution that comprises acquisition, open-FPGA image processing, and a flexible custom camera interface. Off-the-shelf HawkEye solutions include support for Camera Link and CoaXPress cameras. The HawkEye-CL is Camera Link Rev. 2.0 compliant and supports 80-bit Camera Link modes, including 10-bits/8-tap and 8-bit/10-tap modes. The HawkEye-CL family is based on PCIe Gen. 3 x8, providing CPU-free ultra-fast offload capacity of up to 64 Gb/s. Huge data buffers of up to 16 GB fortify the acquisition bandwidth and the image processing capabilities on powerful Arria® 10 FPGAs. The HawkEye is supported by Gidel’s Proc Developer’s kit, which includes the ProcFG GUI application, an API library and examples for developing a customized application, and the ProcWizard application for efficient development of image processing algorithms on FPGA. The HawkEye-CL is also supported by Gidel’s HLS application support package for compiling untimed C++ code to FPGA HDL code using Intel® HLS Compiler as well as the ProcVision Tool Kit
Offering
Gidel’s FantoVision 40™ is a pioneering compact computer enabling image acquisition and processing from 4 x 10GigE or 4 x CoaXPress 2.1 cameras. The FantoVision’s innovative architecture merges high-end image acquisition with real-time image processing and/or compression using an embedded computer with optional pre-processing/compression on Intel® Arria® 10 FPGA. The embedded computer boasts up to 100 TOPS AI compute capability using comprehensive libraries. The GPU and FPGA interconnect via 4-lane PCIe Gen 3. With up to 2 Tera Byte+ SSD, the system can perform demanding real-time processing, compression, and recording. The FPGA is fortified with up to 10 GB DDR4@200 Gb/s. Open Customizable Image Processing: The FantoVision is also distinct in its open architecture enabling embedded AI/image processing on GPU and FPGA. Software engineers can program their algorithms on GPU using C/C++ and AI libraries. In addition, developing and deploying optional pre-processing block on FPGA is simple and fast using Gidel’s novel ProcVision™ Suite. Scalable Solution: The FantoVision opens the way for new compact, cost-effective, scalable vision and imaging solutions for high-bandwidth, low-latency applications. Multi-FantoVision units can be interconnected to provide unique and scalable topologies. Using Gidel’s InfiniVision™ open frame grabber flow, 100+ sensors can be synchronized and processed simultaneously. Note: Intel®, the Intel® logo and Arria® are trademarks of Intel® Corporation or its subsidiaries.
Offering
Gidel’s latest high-performance scalable compute acceleration system, the Proc10S, pushes data processing power to new heights with peak single precision performance of up to 10 TFLOPS. The Proc10S features an Intel® Stratix® 10 FPGA with up 2.8 million logic elements, 260 GB DDR4 memory, and option for SoC Quad-core 64-bit ARM Cortex-A53 MPCore processor . The Proc10S boasts a 16-lane PCIe Gen. 3 host interface and 26 Gb/s and 17.4 Gb/s SERDES I/O transceivers for ultra-fast data injection to the FPGA. Abundant transceiver I/O connectivity enabling a total of 400 Gb/s includes 2x QSFP28, 2x SFP28 and Gidel proprietary high-speed connectors.Intel® Stratix® 10 GX/SX FPGAUp to 2,800K logic elementsFor SX devices, Quad-core 64-bit ARM Cortex-A53 MPCore processorPCIe x16 Gen. 3 or stand-aloneUp to 10× 26 Gb/s + 8x 17.4 Gb/s reconfigurable transceivers (total of 400 Gb/s)Form factor: Full-height, double-width, ¾ length PCI Express cardSupports up to 12V/300W2x QSFP28, 2x SFP28, and Gidel high-speed connectorsMulti-level memory structure (260+ GB):
Offering
TotalHistory IP Core for Signal Tracing Gidel’s Total History IP Core is an innovative signal tracing tool for FPGA prototyping enabling virtually unlimited signal trace depth, and massive and flexible probing of real system performance. TotalHistory uses the unused on-board memory and memory bandwidth of the FPGA boards, thus requires no additional resources. GiDEL’s novel TotalHistory IP opens the way to unprecedented design visibility. TotalHistory is based on a unique design-embedded IP core. Probes are inserted at any design point of interest to capture signals at full operating speed; signal trace is stored in the on-board memory or on peripheral SODIMMs at practically unlimited depth (up to 8.5 GB/FPGA) enabling virtually infinite signal tracing regression to accurately detect, reproduce, and isolate system bugs. Real-time signals are channeled to the host allowing user application processing to generate complex triggering schemes to detect bugs and to capture vital internal signal states. Once a trigger is issued, virtually infinite signal trace history can be retroactively analyzed by the host application, or by a simulator via the PCI/e bridge, or via Gigabit Ethernet (in the case of a PROC_SoCTM system). TotalHistory can support as much as 100,000 fully configurable probes per FPGA permitting comprehensive signal visibility. The TotalHistory IP provides an effective and simple means to probe and to debug complex FPGA designs.
Offering
The Gidel InfiniVision™ frame grabber system provides flexible infrastructure for image acquisition and processing from multiple cameras/sensors simultaneously. The system can capture data streams of varying frame data size and can synchronize between up to 100 cameras/sensors. Camera interfaces currently offered by Gidel include GigE Vision CoaXPress-12, Camera Link, and MIPI, as well as an option for customizing the camera/sensor interface and protocol. The acquisition path allows for adding data processing blocks such as Image Signal Processing (ISP) and compression. The InfiniVision system includes Gidel FPGA frame grabber board(s), IP, API and example software applications. The InfiniVision is offered with open FPGA code that can be customized to user system specifications. The system is supported by Gidel's innovative tools enabling to quickly develop on FPGA, including customization of acquisition flow and embedding used image processing block in the InfiniVision acquisition flow. InfiniVision can be embedded in a variety of FPGAs, including Arria 10, Stratix 10 N/M/S. Product Features: Grabbing and synchronizing from100+ cameras; Grabbing capability of varying incoming data size; Option for adding inline Image Signal Processing (ISP); Option for inline image compression; Support for CoaXPress, Camera Link, and MIPI. Ability to tailor to any camera interface and protocol; Acquisition rate of up to 400 Gb/s per board; Up to 512+ GB image frame buffer; PCIe Gen. 3 x up to 16 lanes; Diverse I/O capabilities: RS422, opto-couplers, LVTTL and 30 V drivers/ receivers; Powerful image processing capabilities on Intel Stratix 10 N/M/S and Arria 10 devices; Supported by the Gidel Developer’s suite for simplifying and accelerating development on FPGA. Support for GenICam GenTL and MVTec’s HALCON machine vision software.