Comcores was founded in 2014 and is a key supplier of digital IP Cores and solutions with a focus on ethernet, wireless and chip-to-chip interfaces. We pride ourselves on providing the best-in-class, quality IP components and systems to ASIC, FPGA, and system vendors. Our core competence is the development and thorough validation of the IPs. By purchasing our IPs, we allow you to focus on your competences, drastically reducing your product cost, risk, and time to market.Our long-term background in mobile communication and being a first-mover in remote radio heads along with expertise in wireless networks gives us a solid foundation for understanding the complex requirements of modern communication tasks. This know-how coupled with 40+ dedicated coworkers/employees/professionals help us define and build state-of-the-art high-quality solutions.
Offerings
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Comcores IEEE 1588 Precision Time Protocol (PTP) Solution is a high quality and high performance time synchronization solution, including Timestamping Unit IP (TSU) and PTP Software Stack. The PTP solution is fully compliant with IEEE 1588 v2.1 and IEEE 1588 v2 standards and enables time synchronization across multiple devices. The solution supports IEEE 802.1AS profile making it ideal for TSN applications. Comcores timing solution supports IEEE 1588 PTP profiles such as IEEE Default and Peer-to-Peer, as well as ITU-T G.8275.1 and ITU-T G.8275.2 profiles. The fully autonomously operated IP includes XGMII and GMII interfaces. User configuration allows easy configuration for various synchronization methods. The PTP solution has been tested successfully at system level thus enabling a fast-track solution for getting started with high performance time synchronization. Time synchronization is crucial in many applications and industries, such as Wireless, Aerospace, Automotive, Industrial, and many others. Phase alignment method allows sub-nanosecond precision and enables even the most demanding applications, for example, 5G networks
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The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b10b encoding. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
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The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
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Comcores Ethernet Subsystem is a silicon-agnostic, easy-to-use integration of 10G/25G Ethernet MAC and PCS for Time-Aware Applications. The Subsystem comes in different variations and can be delivered integrated with Time Stamping Unit, IEEE 1588 PTP Software Stack, and DMA Controller. Comcores Ethernet Subsystem is a richly featured, fully configurable solution delivering best in market performance while still keeping size at a minimum. The subsystem is ready for 5G applications and is thoroughly tested and verified, thus will reduce risk and save development time.
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Comcores Radio Over Ethernet Structure Agnostic Mapper/Demapper IP core is a silicon agnostic implementation of the structure agnostic mapping method described in the IEEE 1914.3 standard. The IP-core takes multiple streams of CPRI data and map these into one or several 10G/25G ethernet data streams and vice versa. The IP core does as well allow for local injection and retraction of ethernet traffic. The IP core allows easy configuration for various synchronization methods and works with CPRI in both slave and master mode. The IP core has been successfully tested in HW and at system level.
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Comcores Ethernet Switch 10G IP core is a highly configurable and size-optimized implementation of a non-blocking switch that allows continuous transmissions between 10G Ethernet ports. The switch supports MAC learning, VLAN 802.1Q, and multicast. Each port provides a native interface for XGMII Ethernet PHY devices.
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Comcores 10G/25G Ethernet MAC and PCS is a silicon agnostic implementation of the IEEE 802.3 Ethernet Layer 2 and PCS layer. The IP core performs the link function of the 10G/25G Ethernet Standard and is a low latency cut-through or store-and-forward implementation reaching best in market results while still keeping size at a minimum. The core is richly featured, fully configurable and supports IEEE1588.
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Comcores Ethernet MAC 40G/100G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited for use in networking equipment such as switches and routers. Comcores Ethernet MAC is silicon-proven and designed for easy integration into ASICs and FPGAs. The Client-side interface is a 128-bit AXI-S and comes with 128-bit XLGMII or CGMII interfaces on the PHY side. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC IP is prepared for easy integration with Comcores Ethernet PCS 40G/100G IP solution.
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Comcores PCS 10G/25G IP core is a silicon agnostic implementation of the PCS layer described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 49 of IEEE 802.3ae specification. The IP-core is part of a family of IP-cores that are tightly integrated. The IP-core has been optimized for size and offers an XGMII/XXVGMII/XLGMII interface on one side and a 10-66-bit parallel interface at the PMA-side.
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Comcores Ethernet MAC 10G/25G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited for use in networking equipment such as switches and routers. Comcores Ethernet MAC is silicon-proven and designed for easy integration into ASICs and FPGAs. The Client-side interface is a 64-bit AXI-S and comes with a 64-bit XGMII interfaces on the PHY side. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC IP is prepared for easy integration with Comcores Ethernet PCS 10G/25G IP solution.
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Comcores Ethernet Switch 1G/10G IP core is a highly configurable and size optimized implementation of a non-blocking crossbar switch that allows continuous transfers between up to four (4) 10 Gbps Ethernet XGMII ports and sixteen (16) 1 Gbps GMII interfaces. The switch supports MAC learning, VLAN 802.1Q, and multicast. It implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking. Each port provides GMII or XGMII native interface for Ethernet PHY devices. The number of ports is configurable at compile time.
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Comcores compact high speed Ethernet switch offers state of the art performance offering four 25 Gbps ports and twelve 10 Gbps ports. The switch supports MAC learning and aging, VLAN 802.1Q, and multicast. It implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking. Each port provides XGMII or XXVMII native interfaces for Ethernet PHY devices.
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Comcores PCS 100G IP core is a silicon agnostic implementation of the PCS layer described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 82 of IEEE 802.3ba and Clause 91 of IEEE 802.3bj specification. The IP-core is part of a family of IIP-cores that are tightly integrated. The IP-core has been optimized for size and offers a CGMII interface on one side and a 4 lane 10-66-bit parallel interface at the PMA-side.
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Comcores Ethernet Switch IP core is a highly configurable and size-optimized implementation of a non-blocking crossbar switch that allows continuous transfers between up to 16 ports Ethernet ports via 1 Gbps GMII interfaces. The switch supports MAC learning and implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking. The switch supports up to 16 ports where each port provides GMII native interface for Ethernet PHY devices. The number of ports is configurable at compile time. Comcores Ethernet Switch IP core is a silicon agnostic implementation targeting both ASICs and FPGAs.
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Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018. The IP-core supports 1G and 2.5G line rates. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent Interface (GMII). On one side it interfaces to a Serdes device and on the application side it has a port for GMII Ethernet signals. The IP-core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
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Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated media access layer. The Interlaken controller can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in number of logic channels (up to 2048), lanes (up to 48) and lane speed (up to 56 Gbps). The IP core is heavily tested in system verilog random regression environment.
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Comcores TSN MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and 802.3br Interspersing Express Traffic. This enables the use of the MAC in high speed time-critical applications. The MAC-core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation, while keeping size at a minimum. The core is fully configurable and interfaces easily to 10G/25G PCS, and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard 64-bit XGMII interface on the PHY side.
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Comcores Ethernet MAC 10M/100M/1G/2.5G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited for use in networking equipment such as switches and routers. Comcores Ethernet MAC is silicon-proven and designed for easy integration into ASICs and FPGAs. The Client-side interface is AXI-S and comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC IP is prepared for easy integration with Comcores Ethernet PCS 10M/100M/1G/2.5G IP solution.
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Comcores Manticore 10M/100M/1G/10G/25G IP is an advanced Ethernet Switch (TSN is optional) with an extensive set of QoS features and statistics. The switch supports up to 8 queues, classification, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparent clock. Each port provides a native interface for Ethernet PHY devices. IEEE 802.1 Protocol Implementation Conformance Statement is available, specifying exact feature-set. It can provide support for key TSN features including IEEE 802.1Qbu and 802.3br Frame preemption, 802.1Qbv Time aware shaping, 802.1Qav Credit based shaping, 802.1Qci Per-Stream Filtering and Policing, and 802.1CB Frame replication and elimination for reliability. This enables the use of the IP in high speed time-critical applications.
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Comcores 10M/100M/1G/2.5G TSN MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption, 802.3br Interspersing Express Traffic, 802.1AS Timing and Synchronization and 802.1Qbv Enhancements for Scheduled Traffic. The TSN MAC enables deterministic low latency and guaranteed bandwidth for time sensitive applications. The TSN MAC allows flexibility in selecting a subset of standards depending on your application from industrial to automotive. The feature rich MAC-core that is delivered with SW API is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and can optionally include features like IEEE1588, VLAN and DMA integration. The Ethernet MAC Core, on the Client side, implements two 8-bit asynchronous FIFO interfaces for Express and Preemptable traffic, respectively while having a standard MII/RGMII/GMII interface on the PHY side.
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Comcores has a solid track record of delivering JESD204B and JESD204C solutions, to support the IPs we offer the verification IP for JESD204, which supports both the JESD204B and JESD204C version. Furthermore, it will support JESD204D (once the standard is published). The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment. The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product. Comcores JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support.