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JESD204C

About this offer

The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.

Details

Regional Coverage

Americas:
Latin America Region
North America Region

Asia, Pacific, and Japan:
Southeast Asia
Australia and New Zealand
Japan
Taiwan
Rest of Asia
Korea
South Asia

Europe, Middle East, and Africa:
Middle East, Turkey, and Africa
Central Eastern Europe
Western European Union Region
Commonwealth of Independent States
Northern European Union Region
Southern European Union Region
Central European Region

People's Republic of China:
People's Republic of China

Use Case

Others

Industry

Others

Communications : Data Processing, Hosting and Related Services

Communications : Publishing (except Internet)

Communications : Telecommunications

Defense and Space

Technical Specifications

Category:
Software and IP Cores: FPGA Intellectual Property Cores: Basic Functions: On-Chip Memory
Operating Systems:

OS Independent:OS Independent family

OS Independent:OS Independent family:OS Independent

End Customer Type:

Small and Medium sized Business

Enterprise

Other

Included Intel Technology

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Stratix® V FPGAs
Stratix® V GS FPGA
Stratix® V GX FPGA
Stratix® V E FPGA
Stratix® V GT FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA
Intel® Arria® 10 GT FPGA
Intel® Cyclone® 10 FPGAs
Intel® Cyclone® 10 LP FPGA
Intel® Cyclone® 10 GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Stratix® IV FPGAs
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 AX SoC FPGA
Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 DX FPGA
Intel® Stratix® 10 SX SoC FPGA
Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 NX FPGA
Cyclone® V FPGAs and SoC FPGAs
Cyclone® V GT FPGA
Cyclone® V SE SoC FPGA
Cyclone® V GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V E FPGA

Resources

JESD204C
Resource Type: URL
Published On: Feb 19, 2022

COMCORES

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COMCORES

Comcores was founded in 2014 and is a key supplier of digital IP Cores and solutions with a focus on ethernet, wireless and chip-to-chip interfaces. We pride ourselves on providing the best-in-class, quality IP components and systems to ASIC, FPGA, and system vendors. Our core competence is the development and thorough validation of the IPs. By purchasing our IPs, we allow you to focus on your competences, drastically reducing your product cost, risk, and time to market.Our long-term background in mobile communication and being a first-mover in remote radio heads along with expertise in wireless networks gives us a solid foundation for understanding the complex requirements of modern communication tasks. This know-how coupled with 40+ dedicated coworkers/employees/professionals help us define and build state-of-the-art high-quality solutions.

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