3. Understanding and Planning Dual Simplex Interfaces
Before starting with your DS mode implementation, determine and plan the simplex IPs (transmitter and receiver) that you want to place in the same transceiver channel. If the simplex IPs in your design do not need to be placed in the same transceiver channel, the DS mode flow described in this document is not applicable and you can proceed to integrate the simplex IPs directly into your RTL design.
- SDI, HDMI and DisplayPort
- SerialLite IV, JESD204C and JESD204B
Upon determining the supported protocol IPs for DS mode, plan how your simplex IPs are paired (transmitter and receiver in the same channel) across the utilized channels. At this point, the planning is based on logical channel placement to establish the DS Group which you can use later for DS IP generation. You can perform the physical pin placement assignment after the IP generation stage.
The following examples illustrate how to plan for the simplex IPs pairing in DS mode to establish a DS Group. A DS Group is defined as a set of simplex IPs that has at least one channel in DS mode.
Example 1: One SDI Transmitter Paired With One SDI Receiver
In this example, one SDI transmitter is paired with one SDI receiver to form a DS group as shown in the following figure.
Example 2: One HDMI Transmitter Paired With One HDMI Receiver
Example 3: One HDMI Transmitter Paired With Two SDI Receivers and a SDI Transmitter
- TX bonding placement—though pairing is based on logical placement, the multi-channel transmitter IPs require bonding, and must meet the physical channel placement requirements as described in Channel Placement for PMA Direct Configuration for Bonded Lane Aggregation figure of the GTS Transceiver PHY User Guide.
- Same System PLL for TX and RX—simplex IPs that are paired in DS mode that use system PLL clocking mode must utilize the same System PLL for that channel. Simplex IPs that use PMA clocking mode can only be paired with another simplex IP with PMA clocking mode. Pairing PMA clocking mode and system PLL mode within a channel is not supported.
- Avalon® memory-mapped interface access—the transmitter and receiver share one Avalon® memory-mapped interface to access each channel. When simplex IPs are paired in DS mode, the generated DS IP includes an Avalon® memory-mapped interface arbiter that retains the individual transmitter IP Avalon® memory-mapped interface and receiver IP Avalon® memory-mapped interface interfaces. This is the same as when you are not using the DS mode.