GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes

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ID 817720
Date 10/07/2024
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1. GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes
1. GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes x
1.1. GTS AXI Streaming Intel® FPGA IP for PCI Express* v6.0.0 1.2. GTS AXI Streaming Intel® FPGA IP for PCI Express* v5.0.0 1.3. GTS AXI Streaming Intel® FPGA IP for PCI Express* v4.0.0
1. GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes

1.1. GTS AXI Streaming Intel® FPGA IP for PCI Express* v6.0.0

Table 1.  v6.0.0 2024.10.07
Quartus® Prime Version Description Impact
24.3 Support for Agilex™ 5 D-Series FPGAs is no longer restricted. Allows you to perform early evaluation of D-Series devices in the Quartus® Prime Pro Edition software.
Reorganized the IP Parameter Editor GUI for the IP. Improves the experience in configuring the IP.
Enabled the following IP features:
  • Hot-Plug
  • Lane Margining
  • Polarity Inversion
  • PCIe 4.0 Retimer
  • Error Interface
  • Configuration Extension Bus
  • Virtio PCI Configuration Access Interface
  • Power Management including Active State Power Management (ASPM)
  • TLP Processing Hints (TPH)
  • Address Translation Services (ATS)
  • Page Request Service (PRS)
  • Access Control Services (ACS)
  • Debug and Performance Monitors
  • Latency Tolerance Reporting (LTR)
 You can now implement these features with the GTS AXI Streaming Intel® FPGA IP for PCI Express* .
Updated the Example Designs with the following support:
  • Added Gen3 x4 PIO design example variant with hardware support.
  • Added board settings for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit.
  • Added Riviera-PRO* and Xcelium* simulator support.
Allows you to get a quick start to evaluate the GTS AXI Streaming Intel® FPGA IP for PCI Express* in simulation and hardware.
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