GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes

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ID 817720
Date 10/07/2024
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1. GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes
1. GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes x
1.1. GTS AXI Streaming Intel® FPGA IP for PCI Express* v6.0.0 1.2. GTS AXI Streaming Intel® FPGA IP for PCI Express* v5.0.0 1.3. GTS AXI Streaming Intel® FPGA IP for PCI Express* v4.0.0
1. GTS AXI Streaming Intel® FPGA IP for PCI Express* Release Notes

1.2. GTS AXI Streaming Intel® FPGA IP for PCI Express* v5.0.0

Table 2.  v5.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2 Added the Eye Viewer feature to the Debug Toolkit in Endpoint mode for Linux and Windows operating systems. You can measure the on-die eye height and width margin.
Added support for PIPE mode simulation for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example. You can enable PIPE mode in addition to FASTSIM mode for faster simulation of the design example. It is recommended to enable both PIPE and FASTSIM modes for optimal simulation time.
Added support for relaxed ordering on the receive side. You can implement relaxed ordering with the GTS AXI Streaming Intel® FPGA IP for PCI Express* .
Added support for Agilex™ 5 D-Series FPGAs1. —
1 Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.
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