GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
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Visible to Intel only — GUID: zsr1711751026299
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2.4.3. PIO Design Example Testbench
The figure below shows the PIO design example simulation design hierarchy.
The tests for the PIO design example are defined with the apps_type_hwtcl parameter set to 3.
- ebfm_cfg_rp_ep_rootport
- find_mem_bar
- downstream_loop
The testbench starts with link training and then accesses the configuration space of the IP for enumeration. A task called downstream_loop (defined in the Root Port PCIe* BFM (altpcietb_bfm_rp_gen4_x16.sv)) then performs the PCIe* link test.
- Issue a memory write command to write a single dword of data into the on-chip memory behind the Endpoint.
- Issue a memory read command to read back data from the on-chip memory.
- Compare the read data with the write data. If they match, the test counts this as a Pass.