GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description 1.3. Performance Design Example 1.4. Performance Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter 1.2.2.8. Soft Reset Controller
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSim* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench 2.4.4. Performance Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.8. Running the Design Example x
2.8.1. Running the PIO Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
A. Appendix

1.4. Performance Design Example Functional Description

  1. GTS AXI Streaming IP for PCI Express* (DUT): This IP is required to incorporate PCI Express* ( PCIe* ) into your design utilizing Altera's advanced PCIe* hardened protocol stack, which encompasses transaction, data link, and physical layers. This component interacts with the root complex/switch at the other end of the PCIe* link and translates the data from the PCIe* link into AXI Stream interface format and vice versa.
  2. Performance Design Example for GTS AXI Streaming IP (perf0): This design example component generates the requested data traffic for throughput measurement. It consists of the following sub-modules:
    1. The AXI_AVST_Interface Adapter converts the single segment 256-bit AXI Transaction Layer Packet (TLP) received from GTS AXI Streaming IP to 512-bit single segment Avalon® -ST TLP. After the conversion, it diverts the TLP to the pioperf_rx_intf or to return CplD tag to the DMA Read in the DMA Top depending on the type of TLP received. The pioperf_rx_diverter module diverts memory write or memory read TLPs from the host and completion TLPs to their respective destinations for further processing.
    2. The pioperf_rx_intf (RX Interface) is a block between the pioperf_rx_diverter and the control register in DMA Top. It decodes the TLP headers and data from the upstream module. It also extracts the information needed to construct the TLP header of the completion data such as the requester ID, tag, attribute, tc and byte count and then passes this to the TX Interface for further processing.
    3. The pioperf_tx_intf (TX Interface) consists of the pioperf_tx_arbiter and the pioperf_tx_slave. It converts the requests from the pioperf_rx_intf and pioperf_dma_top modules into TLPs and sends them to the DUT. The TLPs are transmitted in a simplified weighted round-robin manner with the following priority scheme: completion TLP > memory read TLP > memory write TLP.
    4. The altpcied_512_256_tx_adapter converts the TX Interface output in 512-bit two segments Avalon® -ST format to 256-bit single segment AXI Stream format.
    5. The avst_to_axi_converter converts the Avalon® streaming interface to the AXI Stream interface.
    6. The pioperf_dma_top (DMA Top) module generates memory write and memory read requests and passes them to the pioperf_tx_intf module based on the information in the control register. Every memory read request is tagged to expecting the completion data before timeout to ensure data completeness. The release of memory write and memory read TLPs builds up the traffic at the TX and RX interfaces of the PCIe* link. A throughput counter is included to analyze the overall throughput of the system.
    7. TX Credit Initialization: The back pressure mechanism by the perf0 is done through the credit system. Therefore, the credit value must be declared during the credit initialization stage. An initial TX credit value is captured and is deducted for any TLP sent to the DUT. When the credit reaches zero, the DUT ceases to send further TLP until the credit is returned by the DUT. This block interfaces with the credit signals from the DUT and focuses on initializing and return of the TX credit. For the TX direction, only crdt_init_ack is asserted in the block to complete the initialization stage. The perf0 captures the TX credit during the initialization stage which is initiated by the DUT.
    8. Soft Reset Controller: This module handles the reset and handshake signals of the GTS AXI Streaming IP for graceful entry and exit for each of the resets (cold, warm, etc.) especially when initiated by the host system.
  3. GTS System PLL Clocks Intel® FPGA IP: This IP is required for PCIe* interface implementation on Agilex™ 3 and Agilex™ 5 devices to configure the reference clock for the System PLL. The reference clock to the System PLL must adhere to the following requirements:
    • If compliance with PCIe* link training timing specifications is required, the reference clock to the System PLL must be available and stable before device configuration begins. The reference clock should be derived from an independent and free-running clock source.
    • Alternatively, if the reference clock from the PCIe* link is guaranteed to be available before device configuration begins, you can use it to drive the System PLL. Once the PCIe* link reference clock is running, it can never be allowed to go down.
      Note: For more information, refer to the Implementing the Implementing the GTS System PLL Clocks Intel® FPGA IP section in the GTS Transceiver PHY User Guide.

      Once the reference clock for the System PLL is up, it must be stable and present throughout the device operation and must not go down. If you are not able to adhere to this requirement, you must reconfigure the device.

  4. GTS Reset Sequencer Intel® FPGA IP: This IP must be instantiated for each device side that uses transceivers. Based on your design, you must instantiate one or two instances of the IP.
    • One GTS Reset Sequencer Intel® FPGA IP instance if your design uses transceivers on one side of the device.
    • Two GTS Reset Sequencer Intel® FPGA IP instances if your design uses transceivers on both sides of the device.
    Note: For more information, refer to the Implementing the GTS Reset Sequencer Intel® FPGA IP section in the GTS Transceiver PHY User Guide.
  5. Reset Release Intel® FPGA IP: This IP holds a control circuit in reset until the device has fully entered user mode. The FPGA asserts the INIT_DONE output to signal that the device is in user mode. The Reset Release IP generates an inverted version of the internal INIT_DONE signal to create the nINIT_DONE output that you can use for your design. The nINIT_DONE signal is high until the entire device enters user mode. After nINIT_DONE asserts (low), all logic is in user mode and the device operates normally. You can use the nINIT_DONE signal in one of the following ways:
    • To gate an external or internal reset.
    • To gate the reset input to I/O PLLs.
    • To gate the write enable of your design blocks such as embedded memory blocks, state machines, and shift registers.
    • To synchronously drive the register reset input ports in your design.
    Note: For more information about the Reset Release Intel® FPGA IP, refer to the Device Configuration User Guide: Agilex 5 FPGAs and SoCs.
Figure 6.  Platform Designer System Contents for the GTS AXI Streaming IP Performance Design Example
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