GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 817713
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description 1.3. Performance Design Example 1.4. Performance Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter 1.2.2.8. Soft Reset Controller
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSim* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench 2.4.4. Performance Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.8. Running the Design Example x
2.8.1. Running the PIO Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
A. Appendix

1.1. Programmed Input/Output Design Example

The GTS AXI Streaming IP design example serves as a known established working design to verify the PCIe* link and functionality on the Agilex™ 3 and Agilex™ 5 FPGA boards.

The GTS AXI Streaming PLD clock runs up to 500MHz for PCIe* 4.0 x8 in the Agilex™ 5 D-Series device, 350MHz for PCIe* 4.0 x4 in the Agilex™ 5 E-Series device, and 300MHz in the Agilex™ 3 device with the user interface data width of 512 bits, 256 bits, and 128 bits, respectively. The user application in the design example is using the PLD clock source from the p<n>_coreclkout_hip_toapp to drive the AXI Stream interface or the p<n>_axi_st_clk input clock.

The design example consists of 3 main components:
  • Generated GTS AXI Streaming IP as Endpoint Variant (DUT)
  • Programmable I/O Application (PIO)
  • On-Chip Memory (MEM)

The GTS AXI Streaming IP design under test (DUT) is configured as an Endpoint receiving the PIO transactions from the root complex over the PCIe* link and transferring them to the PIO application module. The TLP received in the PIO application module is decoded and converted into Avalon® memory-mapped interface format. Depending on the received instruction, the on-chip memory is the targeted space to store or read data.

The PIO design example automatically creates the required files for simulation and compilation in the Quartus® Prime software. However, it does not cover all possible GTS AXI Streaming IP parameterizations.

Below are the limitations of the design example:
  • There is no support on the back-to-back TLP packets from the host processor.
  • TLP prefix is not used and intended with Single Physical Function (PF).
  • There is no requirement for error message, interrupt or status bit toggling handling.
  • The backpressure mechanism of the DUT is handled through the ready signal. Besides ready, receive (RX) signals can also be backpressured through p0_app_ss_st_rx_tuser_halt. There is also the (transmit) TX credit mechanism of back pressure.
  • Does not include the full features of the GTS AXI Streaming IP.
Figure 1. PIO Design Example Variant Block Diagram
Level Two Title