GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 817713
Date 5/09/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

1.2.2.1. Scheduler

The data stream from DUT is buffered in the data FIFO within the scheduler block. The header is pre-processed to calculate some prerequisite values. After pre-calculating the write burst count, it passes the command to the Read Write Module and write First DWORD Byte Enable and Last DWORD Byte Enable from the header information.
  • Write sequence: The data in the data FIFO is forwarded to the Read Write Module.
  • Read sequence: Read TLP attributes to generate the completion TLP and additional processing to determine the Type1 and Type2 read. When the TLP DW length is less advanced than the Maximum Payload Size boundary, Type1 read is initiated. When the TLP DW length is larger than the Maximum Payload Size boundary, the Type2 read is initiated. Each Type1 and Type2 read could only hold up to the size of its MPS. Since this is a read sequence, no data in the data FIFO is forwarded to the Read Write Module. Only the pre-processed commands are forwarded to the pre-processed command FIFO for the Avalon® memory-mapped interface generation in the Read Write Module. Only Type1 read is used in this design example.
Level Two Title