GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/09/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* 2.3.2. Steps to Run Simulation using VCS* MX 2.3.3. Steps to Run Simulation using QuestaSim*
2.3.1. Steps to Run Simulation using VCS* x
2.3.1.1. Running VCS* Simulation in Interactive Mode
2.3.2. Steps to Run Simulation using VCS* MX x
2.3.2.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. PIO Design Example Testbench
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.4.2. PIO Design Example Testbench

The figure below shows the PIO design example simulation design hierarchy.

Figure 9. PIO Design Example Simulation Design Hierarchy

The tests for the PIO design example are defined with the apps_type_hwtcl parameter set to 3.

The tests run under this parameter value are defined in the following tasks:
  • ebfm_cfg_rp_ep_rootport
  • find_mem_bar
  • downstream_loop

The testbench starts with link training and then accesses the configuration space of the IP for enumeration. A task called downstream_loop (defined in the Root Port PCIe* BFM (altpcietb_bfm_rp_gen4_x16.sv)) then performs the PCIe* link test.

This test consists of the following steps:
  1. Issue a memory write command to write a single dword of data into the on-chip memory behind the Endpoint.
  2. Issue a memory read command to read back data from the on-chip memory.
  3. Compare the read data with the write data. If they match, the test counts this as a Pass.
Figure 10. PIO Design Example—Memory Write Followed by Memory Read Simulation Waveforms
Figure 11. PIO Design Example—Completion TLP Simulation Waveforms
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