GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

10.3.2. Simulation Output

The following sample output illustrates a successful simulation test run for QuestaSim simulator. The script and waveform output is similar for other supported simulators.

# ---TX reset sequence completed -----
# [STATUS_FSM] (@t = 27966006000) (basic_avl_tb_top.intel_eth_gts_hw.IP_INST[0].hw_ip_top.dut.intel_
eth_gts_0.hip_inst.n_channel_superset_wrapper_inst.n_channel_superset.hal_top_wrapper_inst.
hal_top_ip.one_lane_inst_0.one_lane_hal_top_p0.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.
ch4_phy_inst.x_std_ipfluxtop_uxtop_wrap_0.sf_rtl_ncrypt_inst.<protected>.<producted>)
Finished state change from RESET to S5, R1, W4
# The time now is 30000000000 
# 
# ---RX reset sequence completed -----
# The time now is 40000000000 
# 
# ---IP_INST[  0] Test    0;   ---Total     16 packets to send-----
# ------IP_INST[  0] Start pkt gen TX-----
# ------Checking Packet TX/RX result-----
# ------------   1 packets Sent;     0 packets Received--------
# ------------  16 packets Sent;    16 packets Received--------
# ------ALL   16  packets Sent out---
# ------ALL   16  packets Received---
# ------TX/RX packet check OK---
# 
# ****Starting AVMM Read/Write****
# ====>MATCH!  Read addr = 00000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 
# 
# ====>MATCH!  Read addr = 00100004, ReaddataValid = 1 Readdata = 12153524 Expected_Readdata = 12153524 
# 
# ====>MATCH!  Read addr = 00100008, ReaddataValid = 1 Readdata = c0895e81 Expected_Readdata = c0895e81 
# 
# ====>MATCH!  Read addr = 00100080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
# 
# ====>MATCH!  Read addr = 00300080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
# 
# ====>MATCH!  Read addr = 00000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
# 
# ====>MATCH!  Read addr = 00050014, ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 
# 
# ====>MATCH!  Read addr = 0005001c, ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 
# 
# ====>MATCH!  Read addr = 00050014, ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 
# 
# ====>MATCH!  Read addr = 00050018, ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 
# 
# ====>MATCH!  Read addr = 000a5000, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
# 
# The time now is 50000000000 
# 
# **** AVMM Read/Write Operation Completed for IP_INST[  0]****
# ** Testbench complete
# **
Note: The simulation completion may take a longer time. To confirm that the simulation is progressing successfully, verify the intermediate outputs from the System Console, such as bringing the base and AN/LT IP out of reset, IP reset sequence, AN/LT completion, and others.