Visible to Intel only — GUID: omg1697544349762
Ixiasoft
Visible to Intel only — GUID: omg1697544349762
Ixiasoft
4.6.2. Connect the FlexE and OTN Mode RX Interface
The GTS Ethernet Intel® FPGA Hard IP RX client interface in FlexE and OTN variations is a PCS66 interface.
Connect the RX PCS66 interface (which is a source) to a sink compliant to the PCs66 interface specification. Connect to the interface signals as described in the table below.
Name | Width | Description |
---|---|---|
o_rx_pcs66_d[65:0] | 66 bits (10GE/25GE) |
Receive 66-bit block data on this output bus. The 66-bit data block follows the Ethernet 64b/66b encoding convention. The two least significant bits are sync header and the remaining 64 bits are data.
|
o_rx_pcs66_valid | 1 bit | When asserted, indicates that o_tx_pcs66_d has a valid 66-bit data block. |
o_rx_pcs66_am_valid | 1 bit | Alignment marker indicator. When asserted, Indicates the 66-bit data block on the o_rx_pcs66_d bus is an alignment marker. |
The following waveform shows how to receive the 66b blocks directly from the RX PCS using the PCS mode RX Interface:
The byte order for the PCS66 mode RX interface is the same as the RX MII PCS interface. Bytes flow from least to most significant byte. The first bit received at the line interface is o_rx_pcs66_d[7:0].
The bit order for the PCS66 mode RX interface is the same as the RX MII PCS interface. Bits flow from least to most significant bit. The first bit received at the line interface is o_rx_pcs66_d[0].