GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 10/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 11. Troubleshoot and Diagnose Issues A. Appendix A: Functional Description B. Appendix B: Configuration Registers C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex™ 5 Ethernet Portfolio and Target Applications 1.5. Agilex™ 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex™ 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Simulation Output
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Troubleshoot and Diagnose Issues x
11.1. Enable Diagnostic Lookback Modes 11.2. Troubleshoot the Reset Sequence 11.3. Use Signal Tap Analyzer for Troubleshooting
11.1. Enable Diagnostic Lookback Modes x
11.1.1. Internal Serial Loopback 11.1.2. Enable MAC Loopback 11.1.3. Enable PCS Loopback 11.1.4. Enable External Loopback 11.1.5. Packet Client Loopback
11.2. Troubleshoot the Reset Sequence x
11.2.1. Debug the Power Up Reset Sequence 11.2.2. Debug the TX Reset Entry Sequence 11.2.3. Debug the TX Reset Exit Sequence 11.2.4. Debug the RX Reset Entry Sequence 11.2.5. Debug the RX Reset Exit Sequence 11.2.6. Debug the Auto Recovery Reset Sequence
A. Appendix A: Functional Description x
A.1. Datapath Description A.2. GTS Ethernet Intel® FPGA Hard IP MAC A.3. PCS, OTN, and FlexE Modes A.4. Precision Time Protocol Interface A.5. Auto-Negotiation and Link Training
A.2. GTS Ethernet Intel® FPGA Hard IP MAC x
A.2.1. MAC TX Datapath A.2.2. MAC RX Datapath A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) A.2.4. Link Fault Signaling A.2.5. Order of Ethernet Transmission:
A.2.1. MAC TX Datapath x
A.2.1.1. Insert TX Preamble, Start, and SFD A.2.1.2. Insert Source Address A.2.1.3. Process Length/Type Field A.2.1.4. Pad the Client Frame A.2.1.5. Insert Frame Check Sequence (CRC-32) A.2.1.6. Generate and Insert Inter-Packet Gap
A.2.2. MAC RX Datapath x
A.2.2.1. Process RX Preamble A.2.2.2. Check RX Strict SFD A.2.2.3. Check RX FCS A.2.2.4. Handle RX Malformed Packet A.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames A.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors A.2.2.7. Inter-Packet Gap
A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
A.2.3.1. Conditions Triggering XOFF Frame Transmission A.2.3.2. Conditions Triggering XON Frame Transmission A.2.3.3. Pause Control and Generation Interface A.2.3.4. Pause Control Frame Filtering
A.3. PCS, OTN, and FlexE Modes x
A.3.1. PCS Mode A.3.2. OTN Mode A.3.3. FlexE Mode
A.4. Precision Time Protocol Interface x
A.4.1. Features A.4.2. PTP User Flow A.4.3. Make PTP UI Adjustments A.4.4. Reference Time Interval A.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
A.4.2. PTP User Flow x
A.4.2.1. PTP TX User Flow A.4.2.2. PTP RX User Flow
A.4.3. Make PTP UI Adjustments x
A.4.3.1. Adjust TX UI A.4.3.2. Adjust RX UI
B. Appendix B: Configuration Registers x
B.1. Ethernet Avalon® Memory-Mapped Interface Address Space B.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

3.2. Configure GTS Ethernet Hard IP

Perform the following steps to configure the GTS Ethernet Intel® FPGA Hard IP :
  1. Select Tools > IP Catalog to open the IP Catalog.
  2. Select GTS Ethernet Intel® FPGA Hard IP (Library > Interface Protocols > GTS Ethernet > Intel® FPGA Hard IP ).
  3. Click Add.
  4. Specify a top-level name <your_ip> and the folder for your custom IP variation. The Parameter Editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click Create. The IP parameter editor appears as shown in the figure below. The GTS Ethernet Intel® FPGA Hard IP has an IP tab, Example Design tab, and Analog Parameters tab.
    Figure 4.  GTS Ethernet Intel® FPGA Hard IP Parameters: IP Tab
  6. On the IP tab, specify the parameters for your IP core variation. Refer to the table below for information about specific IP core parameters.
Table 12.   GTS Ethernet Intel® FPGA Hard IP Parameters
Parameter Range Default Setting Parameter Description
Auto-Negotiation and Link Training Options
Enable auto-negotiation and link training
  • Enable
  • Disable
 Disable When selected, the IP includes additional soft logic to perform Auto-Negotiation and Link Training (AN/LT).
Simulation Options
Enable Fast Simulation
  • Enable
  • Disable
 Enable Enables fast simulation in the generated example design for Ethernet IP, and also enables fast simulation in AN/LT IP, if AN/LT is enabled.
Note: If fast simulation is enabled, the GTS Ethernet Intel® FPGA Hard IP skips auto-negotiation and link training functionality and updates the AN/LT status registers to reflect AN/LT completion. To exercise complete AN/LT functionality during simulation, disable the fast simulation option.
IP Tab : General Options
Client interface
  • MAC Avalon® ST
  • MII PCS Only
  • PCS66 OTN
  • PCS66 FlexE
 MAC Avalon® ST
Selects data interface exposed to a client. Selected interface determines the Ethernet functional blocks enabled in the design.
  • MAC Avalon® streaming interface for 10GE Ethernet.
  • PCS66 Interface for OTN and FlexE
PMA Reference frequency
  • 156.250000
  • 322.265625
  • 312.500000
 156. 250000
Selects the reference clock frequency used by the transceiver.
  • 156.25 MHz is the recommended frequency for 10GE Ethernet mode.
  • 312.5 MHz is also supported when AN/LT is not used.
  • The frequency 322.265625 MHz is supported when you select IEEE 802.3 BASE-R Firecode or RS(528,514), while using without AN/LT.
System PLL frequency
  • 322.265625
  • 805.664062
  • Custom
 322.265625
Selects the System PLL frequency. The core clock (o_clk_pll) is equivalent to this rate divided by 2.
  • 322.265625 MHz for 10GE Ethernet Mode.
  • 805.664062 MHz for 25GE Ethernet mode.
Custom System PLL Frequency 322.265625 - 1000
  • 536.2500000
  • 805.6640625
 If you choose the Custom option in the System PLL Frequency parameter, the IP core clock (o_clk_pll) is equivalent to half of the specified rate.
  • 536.2500000: Agilex™ 5 E-Series (Device Group B).
  • 805.6640625: Agilex™ 5 E-Series (Device Group A) and D-series.
Enable Dedicated CDR Clock Output
  • Enable
  • Disable
 Disable When selected, enables the dedicated CDR clock output. Each bank has only one such dedicated output.
PTP Options Tab
Enable IEEE 1588 PTP
  • Enable
  • Disable
 Disable Enable this option to add IEEE 1588 PTP Timestamp offload functions to the Core. The core can generate one-step or two-step TX and RX timestamps.
Timestamp fingerprint width
  • 8
  • 32
 8 Specify the timestamp fingerprint width in bits on the TX path. The default value is 8 bits.
Base_Port > Port #0 IP Configuration
Ethernet Mode
  • 10G-1
  • 25G-1
 10G-1 This option defines serial line rate.
FEC Mode
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.2 RS(528,514) (CL 91)
 None
Selects the FEC mode for each port.
  • Firecode FEC only supported for 10GE Ethernet Mode.
  • RS(528,514) only supports 25GE Ethernet mode.
Base_Port(Port #0) > Port #0 IP Configuration > Port #0 MAC Option > P0 BasicBase
Ready latency 0 - 3 0

Selects the ready Latency value on the TX client interface.

Ready Latency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the o_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon® Interface Specifications.

Enable asynchronous adapter clocks
  • Enable
  • Disable
 Disable

When turned on, you may drive the i_clk_rx and i_clk_tx clock signals different from o_clk_pll clock.

Available only when Client interface is set to MAC Avalon® streaming interface.

TX Maximum Frame size 65 - 65,535 1518 Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.
RX Maximum Frame size 65 - 65,535 1518

Maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters.

RX Frames larger than TX Maximum frame size are treated as oversized.

If you turn on Enforce Maximum Frame Size parameter, the IP core truncates incoming Ethernet packets that exceed this size.

Enforce maximum frame size
  • Enable
  • Disable
 Disable Specifies whether the IP core can receive an oversized packet or truncates these packets. In a truncated packet, error signal indicates oversize and FCS error.
Link fault generation option
  • OFF
  • Unidirectional
  • Bidirectional
 OFF

Specifies the IP core response to link fault events. Bidirectional link fault handling complies with the Ethernet specification, specifically IEEE 802.3 Figure 81-11.

Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets.

The OFF option is provided for backward compatibility.

Bytes to remove from RX frames
  • None
  • Remove CRC bytes.
  • Remove CRC and PAD bytes
 None Selects whether the RX MAC must remove CRC bytes, or retain all bytes in incoming RX frames before passing them to the RX MAC Client. If the PAD bytes and CRC are not needed downstream, this option can reduce the need for downstream packet processing logic.
Forward RX pause requests
  • Enable
  • Disable
 Disable

Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface or drops them after internal processing.

Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing. In that case this parameter has no effect.
Use source address insertion
  • Enable
  • Disable
 Disable

Selects whether the IP core supports overwriting the source address in an outgoing Ethernet packet with the value in the TXMAC_SADDR registers.

If the parameter is turned on, the IP core overwrites the packet source address from the register if i_tx_skip_crc has the value of 0.

If the parameter is turned off, the IP core does not overwrite the source address. Source address insertion applies to PAUSE and PFC packets provided on the TX MAC client interface but does not apply to PAUSE and PFC packets the IP core transmits in response to the assertion of i_tx_pause or i_tx_pfc[n] on the TX MAC client interface.

TX MAC Source Address String “001122334455”

TX MAC Source Address default value to use as Source Address for TX PAUSE/PFC packets and when Use Source Address Insertion is enabled.

Value is a 48-bit number written in Hexadecimal.
TX VLAN detection
  • Enable
  • Disable

Enable

Specifies whether the IP core TX statistics block treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frames in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the TxFrameOctetsOK counter.

If turned on, the IP core identifies these frames in TX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.

RX VLAN detection
  • Enable
  • Disable

Enable

Specifies whether the IP core RX statistics block treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frames in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the RxFrameOctetsOK counter.

If turned on, the IP core identifies these frames in RX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.

Stop TX traffic when link partner sends PAUSE
  • No
  • Yes
  • Disable flow control
 No

When set to Yes, both SFC and PFC are supported. When a pause frame is received, the TX MAC stops sending traffic.

When set to No, both SFC and PFC are supported. When a pause frame is received, the TX MAC does not stop sending traffic. When set to Disable, flow control is disabled entirely.

Base_Port(Port #0) > Port #0 IP Configuration > Port #0 MAC Option > P0 Specialized
Enable strict preamble check
  • Enable
  • Disable
 Disable

If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Enable strict SFD check
  • Enable
  • Disable
 Disable

If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).
Average Interpacket Gap
  • 1
  • 8
  • 10
  • 12
 12 Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link. Specifies the average minimum Inter-Packet Gap (IPG) the IP core maintains on the TX Ethernet link. The default value of 12 complies with the Ethernet standard. The remaining values support increased throughput. The value of 1 specifies that the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. The IP core no longer complies with the Ethernet standard, but the application has control over the average gap and maximizing the throughput.
Enable preamble passthrough
  • Enable
  • Disable
 Disable

If turned on, the IP core is in RX and TX preamble pass-through mode.

In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet.

In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.
Base_Port(Port #0) > Port #0 IP Configuration > Configurations, Debug and Extension Options
Enable debug endpoint for transceiver toolkit
  • Enable
  • Disable
 Disable Enables the Transceiver toolkit.

When enabled, an embedded Native Phy Debug Endpoint connects internally to the AVMM slave interface for the use of transceiver toolkit.

Enable debug endpoint for Ethernet toolkit
  • Enable
  • Disable
 Disable

Enables the Ethernet toolkit

When enabled, an embedded Ethernet Debug Endpoint connects internally to the AVMM slave for the use of Ethernet toolkit.
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