GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

5.6.1. Example Use Case 1

In this example use case, both sides of the device are fully populated and have the following IPs instantiated:
  • Two GTS Reset Sequencer Intel FPGA IP
  • Four GTS PMA/FEC Direct PHY Intel FPGA IP
  • One GTS Ethernet Intel FPGA Hard IP
  • One GTS PCI Express* Intel FPGA IP
  • One Triple-Speed Ethernet Intel FPGA IP
  • One HPS USB3.1
Table 75.  GTS Reset Sequencer Intel FPGA IP Parameter Settings for Use Case 1
GTS Reset Sequencer Intel FPGA IP Parameter Value Selection
# 1 (Left Side) Enable PCIE and/or HPS USB3.1 only design Off
Number of Reset Sequencer Lane(s) 11
Number of Bank(s) 3
# 2 (Right Side) Enable PCIE and/or HPS USB3.1 only design Off
Number of Reset Sequencer Lane(s) 8
Number of Bank(s) 3
The following figure shows the connections between the two GTS Reset Sequencer Intel FPGA IPs and the other instantiated IPs.
Figure 79. Example Use Case 1