GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

Visible to Intel only — GUID: utw1664999634094

Ixiasoft

Document Table of Contents

2.3.1.3. Data Pattern Generator and Verifier

The PMA supports a built-in PRBS data pattern generator and verifier.
You can use the built-in PRBS generator and verifier patterns to perform design for test checks by generating the PHY data traffic. This feature allows you to debug the PMA without needing the upper protocol hard IP layers. The pattern and size are programmable. The supported programmable PRBS patterns are shown below:
  • PRBS31
  • PRBS23
  • PRBS15
  • PRBS13
  • PRBS10
  • PRBS9
  • PRBS7
The data pattern verifier contains a receiver built-in self-test (BIST) bit error checker. The receiver can check standard data patterns for link verification applications by enabling the PRBS mode in both the receiver link and a compatible transmitter link connected by a common transmission path or loopback.