External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

12.9. Hardware Debugging Guidelines

Before debugging your design, confirm that it follows the recommended design flow. Refer to the Agilex™ 5 EMIF IP Design Flow section in chapter 1 of this user guide.

Always keep a record of tests, to avoid repeating the same tests later. To start debugging the design, perform the following initial steps.