External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs
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- 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
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13.2.2. Example 2: Reading the Memory Clock Frequency for an Interface
The values in this example are for illustrative purposes and are obtained from an EMIF example design with DDR4 x32 + ECC running at 800MHz on the Agilex™ 5 FPGA E-Series 065B Development Kit - Premium. This configuration uses the Primary MC of the Primary IO96B.
Base address=0x500_0000
Address for each read-only register = Base address + offset of each register
Register Name | Byte Offset (Hexadecimal) | Address (Hexadecimal) |
---|---|---|
MEMCLK_FREQ_FSP_CUR_INTF0 | 0x220 | 0x5000220 |
The expected read_data=0x000c_3500