External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Agilex™ 5 FPGA EMIF IP - Mailbox Support 14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4 4.6. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. s1_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s1_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s1_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. mem_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_ck_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_i3c for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. oct_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4 x
4.5.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR4
4.6. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5 x
4.6.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.4. Agilex™ 5 EMIF Pin Swapping Guidelines
6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 5 FPGA EMIF IP Resources 6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.3.1. Agilex™ 5 FPGA EMIF IP Resources x
6.3.1.1. OCT 6.3.1.2. PLL
6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.3.2.1.2. Estimating Pin Requirements 6.3.2.1.3. Maximum Number of Interfaces
6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.3.3.1. Address and Command Pin Placement for DDR4 6.3.3.2. DDR4 Data Width Mapping 6.3.3.3. General Guidelines 6.3.3.4. x4 DIMM Implementation 6.3.3.5. Specific Pin Connection Requirements 6.3.3.6. Command and Address Signals 6.3.3.7. Clock Signals 6.3.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.4.1. DDR4 Byte Lane Swapping 6.4.2. DDR4 Address and Command and CLK Lane 6.4.3. DDR4 Interface x8 Data Lane 6.4.4. DDR4 Interface x4 Data Lane
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. PHY DFE Tap Bias Values for DDR5 7.4. MEM DFE Tap Bias Values for DDR5 7.5. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.5. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.5.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.5.2. Agilex™ 5 FPGA EMIF IP Resources 7.5.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.5.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.5.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.5.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.5.1.1. Estimating Pin Requirements 7.5.1.2. DIMM Options 7.5.1.3. Maximum Number of Interfaces
7.5.2. Agilex™ 5 FPGA EMIF IP Resources x
7.5.2.1. OCT 7.5.2.2. PLL
7.5.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.5.3.1. General Guidelines - DDR5 7.5.3.2. x4 DIMM Implementation 7.5.3.3. Specific Pin Connection Requirements 7.5.3.4. Command and Address Signals 7.5.3.5. Clock Signals 7.5.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.5.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.5.4.1. Address and Command Pin Placement for DDR5 7.5.4.2. DDR5 Data Width Mapping
7.5.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.5.5.1. DDR5 Byte Lane Swapping 7.5.5.2. DDR5 Address and Command and CLK Lane 7.5.5.3. DDR5 Interface x8 Data Lane 7.5.5.4. DDR5 Interface x4 Data Lane 7.5.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR4 Parameter Descriptions 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 9.2. PHY DFE Tap Bias Values for LPDDR5 9.3. MEM DFE Tap Bias Values for LPDDR5 9.4. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
9.4. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.4.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.4.2. Agilex™ 5 FPGA EMIF IP Resources 9.4.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.4.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.4.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.4.1.1. Estimating Pin Requirements 9.4.1.2. LPDDR5 Component Options 9.4.1.3. Maximum Number of Interfaces
9.4.2. Agilex™ 5 FPGA EMIF IP Resources x
9.4.2.1. OCT 9.4.2.2. PLL
9.4.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.4.3.1. General Guidelines - LPDDR5 9.4.3.2. Specific Pin Connection Requirements 9.4.3.3. Command and Address Signals 9.4.3.4. Clock Signals
9.4.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.4.4.1. Address and Command Pin Placement for LPDDR5 9.4.4.2. LPDDR5 Data Width Mapping 9.4.4.3. LPDDR5 Byte Lane Swapping
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support x
13.1. Agilex™ 5 Mailbox Structure and Register Definitions 13.2. Sending a Mailbox Command
13.1. Agilex™ 5 Mailbox Structure and Register Definitions x
13.1.1. Mailbox Supported Commands 13.1.2. Mailbox Command Definitions 13.1.3. ECC Syndrome Codes
13.2. Sending a Mailbox Command x
13.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox 13.2.2. Example 2: Reading the Memory Clock Frequency for an Interface 13.2.3. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support
14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP.
Table 148.  Group: High-level Configuration / Memory Device
Parameter Name Description
Number of Channels

Specifies the number of channels that the interface should implement. For multi-channel devices, this should always match the number of channels on the device.

Default value is 1

Legal values are: 1, 2

(Identifier: MEM_NUM_CHANNELS)
Data DQ Width

Number of DQ pins per memory channel, used for data.

Default value is 32

Legal values are: 16, 32, 40

(Identifier: MEM_CHANNEL_DATA_DQ_WIDTH)
ECC DQ Width

Number of additional DQ pins per memory channel, used for out-of-band ECC. If bigger than 0, controller will enable out-of-band ECC. Otherwise, out-of-band ECC will be disabled.

Default value is 0

Legal values are: 0, 8

(Identifier: MEM_CHANNEL_ECC_DQ_WIDTH)
Die DQ Width

Number of DQ pins in each die that makes up the interface. For dual-die packages, this is the width of the die, not the width of full the package.

Default value is 16

Legal values are: 8, 16

(Identifier: MEM_DIE_DQ_WIDTH)
Die Density

Capacity of each memory die (in Gbits), per channel per die. For dual-die packages, this is the density of each die, not the density of the full package.

Default value is 8

Legal values are: 8, 16, 24, 32

(Identifier: MEM_DIE_DENSITY_GBITS)
CS Width

Specifies the total number of CS pins used by each channel.

Default value is 1

Legal values are: 1, 2

(Identifier: MEM_CHANNEL_CS_WIDTH)
Memory Speedbin

Specifies the speedbin of the memory device(s) of which the interface consists.

Default value is 5600AN

Legal values are: 3200AN, 3200B, 3200BN, 3200C, 3600AN, 3600B, 3600BN, 3600C, 4000AN, 4000B, 4000BN, 4000C, 4400AN, 4400B, 4400BN, 4400C, 4800AN, 4800B, 4800BN, 4800C, 5200AN, 5200B, 5200BN, 5200C, 5600AN, 5600B, 5600BN, 5600C

(Identifier: MEM_SPEEDBIN)
Auto-set Memory Operating Frequency

if true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency

Specifies the frequency at which the memory interface will run.

Legal values are: 1600, 1800, 2000, 2200, 2400, 2600, 2800

(Identifier: MEM_OPERATING_FREQ_MHZ)
Table 149.  Group: High-level Configuration / PHY
Parameter Name Description
Auto-set PLL Reference Clock Frequency

if true, let IP select max PLL refclk frequency that this configuration can support. If false, user can set custom value for PLL refclk frequency.

Default value is true

(Identifier: PHY_REFCLK_FREQ_MHZ_AUTOSET_EN)
Enable Advanced List of PLL Reference Clock Frequencies

If true, provide extended list of possible refclk values. Otherwise, prune possible list of refclk values to a more reasonable length.

Default value is false

(Identifier: PHY_REFCLK_ADVANCED_SELECT_EN)
Reference Clock Frequency

Specifies the reference clock frequency for the EMIF IOPLL.

(Identifier: PHY_REFCLK_FREQ_MHZ)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms I/O BANK and TOP vs BOT part of the I/O BANK). Legal ranges are derived from device floorplan.

Default value is BOT

Legal values are: BOT, TOP, FULL

(Identifier: PHY_AC_PLACEMENT)
Auto-set Mainband Access Mode

if true, let IP select most likely usecase for the PHY_MAINBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN)
Mainband Access Mode

Specifies the path through which the EMIF QHIP mainband interface is exposed to the user. The mainband interface is the AXI4 interface to the memory controller.

Legal values are: NOC, ASYNC, SYNC

(Identifier: PHY_MAINBAND_ACCESS_MODE)
Auto-set Sideband Access Mode

if true, let IP select most likely usecase for the PHY_SIDEBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN)
Sideband Access Mode

Specifies the path through which the EMIF QHIP sideband interface is exposed to the user. The sideband interface is the AXI4-Lite interface to the IOSSM.

Legal values are: NOC, FABRIC

(Identifier: PHY_SIDEBAND_ACCESS_MODE)
Pin Swizzle Map

Specifies the swizzle map for the data lanes and pins.

(Identifier: PHY_SWIZZLE_MAP)
Use Debug Toolkit

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

Default value is false

(Identifier: DEBUG_TOOLS_EN)
Instance ID

Instance ID of the EMIF IP. This is useful when using a discovery mechanism over the side-band interface, to identify which EMIF instance's mailbox is at which offset. If expecting to use a discovery mechanism in hardware, this parameter must be set uniquely for all EMIFs that share a sideband. Otherwise, this parameter can be ignored / kept at the default value.

Default value is 0

Legal values are: from 0 to 6

(Identifier: INSTANCE_ID)
Table 150.  Group: High-level Configuration / Controller
Parameter Name Description
Use ECC Autocorrection

If ECC is enabled, specifies whether single-bit-errors (SBEs) should be corrected or just reported.

Default value is true

(Identifier: CTRL_ECC_AUTOCORRECT_EN)
Use Data Masking

Specifies whether Data Masking is enabled by the controller. When ECC is enabled, RMWs will occur (to recompute / write ECC), regardless of whether this is enabled.

Default value is false

(Identifier: CTRL_DM_EN)
Table 151.  Group: Advanced: Memory Timing / Overrides / JEDEC_TABLE
Parameter Name Description
JEDEC Parameter

Name of JEDEC Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: MEM_OPERATING_SPEEDBIN, MEM_CL_CYC, MEM_CWL_CYC, MEM_WR_PREAMBLE_MODE, MEM_RD_PREAMBLE_MODE, MEM_WR_POSTAMBLE_MODE, MEM_RD_POSTAMBLE_MODE, MEM_FINE_GRANULARITY_REFRESH_MODE, MEM_TREFI1_NS, MEM_TREFI2_NS, MEM_TREFISB_NS, MEM_TCCD_S_CYC, MEM_TCCD_L_NS, MEM_TCCD_L_WR_NS, MEM_TCCD_L_WR2_NS, MEM_TRRD_S_CYC, MEM_TRRD_L_NS, MEM_TFAW_NS, MEM_TRFC1_NS, MEM_TRFC2_NS, MEM_TRFCSB_NS, MEM_TRCD_NS, MEM_TRP_NS, MEM_TRAS_NS, MEM_TRC_NS, MEM_TREFSBRD_NS, MEM_TWR_NS, MEM_TZQLAT_NS, MEM_TZQCAL_NS, MEM_TMRR_NS, MEM_TMRR_P_NS, MEM_TMRW_NS, MEM_TMRD_NS, MEM_TDFE_NS, MEM_TDLLK_NS, MEM_TWTR_S_NS, MEM_TWTR_L_NS, MEM_TRTP_NS, MEM_TPPD_CYC, MEM_TPD_NS, MEM_TACTPDEN_CYC, MEM_TPRPDEN_CYC, MEM_TREFPDEN_CYC, MEM_TXP_NS, MEM_TCPDED_CYC, MEM_TCSL_NS, MEM_TCKSRX_NS, MEM_TCSH_SREXIT_NS, MEM_TDQSCK_MIN_CYC, MEM_TDQSCK_MAX_CYC, MEM_TDQSCK_CYC, MEM_TWPRE_EN_CYC, MEM_TDQSS_CYC, MEM_TCKLCS_CYC, MEM_TWTRA_NS

(Identifier: JEDEC_OVERRIDE_TABLE_PARAM_NAME)
Table 152.  Group: Advanced: Memory Timing / Values
Parameter Name Description
Operating Speedbin

Specifies the operating speedbin of the memory device(s) for the current operating frequency and device speedbin.

(Identifier: MEM_OPERATING_SPEEDBIN)
Read Latency

Read Latency of the memory device in clock cycles.

(Identifier: MEM_CL_CYC)
Write Latency

Write Latency in clock cycles.

(Identifier: MEM_CWL_CYC)
Write Preamble Mode

Specifies the write preamble mode of the memory interface (0: not supported, 1: 2-cycle preamble, 2: 3-cycle preamble, 3: 4-cycle preamble).

(Identifier: MEM_WR_PREAMBLE_MODE)
Read Preamble Mode

Specifies the read preamble mode of the memory interface (0: 1-cycle preamble, 1: 2-cycle preamble, 2: 2-cycle DDR4-style preamble, 3: 3-cycle preamble, 4: 4-cycle preamble).

(Identifier: MEM_RD_PREAMBLE_MODE)
Write Postamble Mode

Specifies the write postamble mode of the memory interface (0: 0.5-cycle postamble, 1: 1.5-cycle postamble).

(Identifier: MEM_WR_POSTAMBLE_MODE)
Read Postamble Mode

Specifies the read postamble mode of the memory interface (0: 0.5-tCK postamble, 1: 1.5-tCK postamble).

(Identifier: MEM_RD_POSTAMBLE_MODE)
Memory Fine Granularity Refresh Mode

Specifies the Fine Granularity Refresh (FGR) mode of the memory interface.

(Identifier: MEM_FINE_GRANULARITY_REFRESH_MODE)
tREFI1

Specifies the maximum average refresh interval in normal refresh mode in nanoseconds.

(Identifier: MEM_TREFI1_NS)
tREFI2

Specifies the maximum average refresh interval in fine granularity refresh mode in nanoseconds.

(Identifier: MEM_TREFI2_NS)
tREFISB

Specifies the maximum average refresh interval in fine granularity and same bank refresh mode in nanoseconds.

(Identifier: MEM_TREFISB_NS)
tCCD_S

Specifies the CAS_n to CAS_n command delay for different bank group in cycles.

(Identifier: MEM_TCCD_S_CYC)
tCCD_L

Specifies the CAS_n to CAS_n command delay for same bank group in nanoseconds.

(Identifier: MEM_TCCD_L_NS)
tCCD_L_WR

Specifies the write CAS_n to write CAS_n command delay for same bank group in nanoseconds.

(Identifier: MEM_TCCD_L_WR_NS)
tCCD_L_WR2

Specifies the write CAS_n to write CAS_n command delay for same bank group and the second write is not RMW, in nanoseconds.

(Identifier: MEM_TCCD_L_WR2_NS)
tRRD_S

Specifies the Activate-to-Activate command delay to different bank group for 1KB page size in nanoseconds.

(Identifier: MEM_TRRD_S_CYC)
tRRD_L

Specifies the Activate-to-Activate command delay to same bank group for 1KB page size in nanoseconds.

(Identifier: MEM_TRRD_L_NS)
tFAW

Specifies the four activate window for 1KB page size in nanoseconds.

(Identifier: MEM_TFAW_NS)
tRFC1

Specifies the refresh operation delay in normal refresh mode in nanoseconds.

(Identifier: MEM_TRFC1_NS)
tRFC2

Specifies the refresh operation delay in fine granularity refresh mode in nanoseconds.

(Identifier: MEM_TRFC2_NS)
tRFCSB

Specifies the refresh operation delay in fine granularity and same bank refresh mode in nanoseconds.

(Identifier: MEM_TRFCSB_NS)
tRCD

Specifies the Activate-to-internal-Read-or-Write delay in nanoseconds.

(Identifier: MEM_TRCD_NS)
tRP

Specifies the row precharge time in nanoseconds.

(Identifier: MEM_TRP_NS)
tRAS

Specifies the Activate-to-Precharge command period in nanoseconds.

(Identifier: MEM_TRAS_NS)
tRC (tRAS+tRP)

Specifies the Activate-to-Activate or Refresh command period in nanoseconds.

(Identifier: MEM_TRC_NS)
tREFSBRD

Specifies the same bank refresh to activate delay in nanoseconds.

(Identifier: MEM_TREFSBRD_NS)
tWR

Specifies the write recovery time in nanoseconds.

(Identifier: MEM_TWR_NS)
tZQLAT

Specifies the ZQ calibration latch time in nanoseconds.

(Identifier: MEM_TZQLAT_NS)
tZQCAL

Specifies the ZQ calibration time in nanoseconds.

(Identifier: MEM_TZQCAL_NS)
tMRR

Specifies the Mode Register Read (MRR) command period in nanoseconds.

(Identifier: MEM_TMRR_NS)
tMRR_P

Specifies the Mode Register Read (MRR) pattern to mode register read pattern command spacing in nanoseconds.

(Identifier: MEM_TMRR_P_NS)
tMRW

Specifies the Mode Register Write (MRW) command period in nanoseconds.

(Identifier: MEM_TMRW_NS)
tMRD

Specifies the Mode Register Set (MRS) command delay in nanoseconds.

(Identifier: MEM_TMRD_NS)
tDFE

Specifies the Decision Feedback Equalization (DFE) Mode Register Write update delay time in nanoseconds.

(Identifier: MEM_TDFE_NS)
tDLLK

Specifies the timing of DLLK in nanoseconds.

(Identifier: MEM_TDLLK_NS)
tWTR_S

Specifies the delay from start of internal write transaction to internal read command for different bank group in nanoseconds.

(Identifier: MEM_TWTR_S_NS)
tWTR_L

Specifies the delay from start of internal write transaction to internal read command for same bank group in nanoseconds.

(Identifier: MEM_TWTR_L_NS)
tRTP

Specifies the internal read command to precharge command delay in nanoseconds.

(Identifier: MEM_TRTP_NS)
tPPD

Specifies the Precharge-to-Precharge delay in cycles.

(Identifier: MEM_TPPD_CYC)
tPD

Specifies the minimum power down time in nanoseconds.

(Identifier: MEM_TPD_NS)
tACTPDEN

Specifies the timing of Activate command to power down entry command in cycles.

(Identifier: MEM_TACTPDEN_CYC)
tPRPDEN

Specifies the timing of Precharge All Banks (PREab), Precharge Same Bank (PREsb), or Normal Precharge (PREpb) to power down entry command in cycles.

(Identifier: MEM_TPRPDEN_CYC)
tREFPDEN

Specifies the timing of Refresh All Banks (REFab) or Refresh Same Bank (REFsb) command to power down entry command in cycles.

(Identifier: MEM_TREFPDEN_CYC)
tXP

Specifies the exit power down to next valid command in nanoseconds.

(Identifier: MEM_TXP_NS)
tCPDED

Specifies the command pass disable delay in nanoseconds.

(Identifier: MEM_TCPDED_CYC)
tCSL

Specifies the Self-Refresh CS_n low pulse width in nanoseconds.

(Identifier: MEM_TCSL_NS)
tCKSRX

Specifies the valid clock requirement before SRX in nanoseconds.

(Identifier: MEM_TCKSRX_NS)
tCSH_SREXIT

Specifies the self-refresh exit CS_n high pulse width in nanoseconds.

(Identifier: MEM_TCSH_SREXIT_NS)
tDQSCK_MIN

Specifies the minimum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

(Identifier: MEM_TDQSCK_MIN_CYC)
tDQSCK_MAX

Specifies the maximum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

(Identifier: MEM_TDQSCK_MAX_CYC)
tDQSCK

Specifies the DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

(Identifier: MEM_TDQSCK_CYC)
tWPRE_EN

Specifies the write preamble enable window in cycles. The window size depends on the write preamble mode.

(Identifier: MEM_TWPRE_EN_CYC)
tDQSS

Specifies the host and system voltage/temperature drift window of first rising DQS_t preamble edge relative to CAS Write Latency (CWL) CK_t-CK_c edge in cycles.

(Identifier: MEM_TDQSS_CYC)
tCKLCS

Specifies the valid clock requirement after SRE in cycles.

(Identifier: MEM_TCKLCS_CYC)
tWTRA

Specifies the delay from start of internal write transaction to internal read with auto precharge command for same bank in nanoseconds.

(Identifier: MEM_TWTRA_NS)
Table 153.  Group: Advanced: Analog Overrides / Overrides / ANALOG_TABLE
Parameter Name Description
Analog Parameter

Name of Analog Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are: PHY_TERM_X_R_S_AC_OUTPUT_OHM, PHY_TERM_X_R_S_CK_OUTPUT_OHM, PHY_TERM_X_R_S_DQ_OUTPUT_OHM, PHY_TERM_X_DQ_SLEW_RATE, PHY_TERM_X_R_T_DQ_INPUT_OHM, PHY_TERM_X_DQ_VREF, PHY_TERM_X_R_T_REFCLK_INPUT_OHM, PHY_DFE_X_TAP_1, PHY_DFE_X_TAP_2, PHY_DFE_X_TAP_3, PHY_DFE_X_TAP_4, MEM_ODT_DQ_X_TGT_WR, MEM_ODT_DQ_X_NON_TGT_WR, MEM_ODT_DQ_X_NON_TGT_RD, MEM_ODT_DQ_X_IDLE, MEM_ODT_DQ_X_RON, MEM_VREF_DQ_X_VALUE, MEM_ODT_CA_X_CA, MEM_ODT_CA_X_CS, MEM_ODT_CA_X_CK, MEM_VREF_CA_X_CA_VALUE, MEM_VREF_CA_X_CS_VALUE, MEM_DFE_X_TAP_1, MEM_DFE_X_TAP_2, MEM_DFE_X_TAP_3, MEM_DFE_X_TAP_4

(Identifier: ANALOG_PARAM_DERIVATION_PARAM_NAME)
Table 154.  Group: Advanced: Analog Overrides / Values
Parameter Name Description
AC Drive Strength

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_34_OHM_CAL, SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_AC_OUTPUT_OHM)
CK Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_34_OHM_CAL, SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_CK_OUTPUT_OHM)
FPGA DQ Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: SERIES_34_OHM_CAL, SERIES_40_OHM_CAL

(Identifier: PHY_TERM_X_R_S_DQ_OUTPUT_OHM)
DQ Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

Legal values are: SLOW, MEDIUM, FAST, FASTEST

(Identifier: PHY_TERM_X_DQ_SLEW_RATE)
DQ Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: RT_40_OHM_CAL, RT_50_OHM_CAL, RT_60_OHM_CAL

(Identifier: PHY_TERM_X_R_T_DQ_INPUT_OHM)
DQ Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

Legal values are: from 0 to 100

(Identifier: PHY_TERM_X_DQ_VREF)
PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are: RT_OFF, RT_DIFF

(Identifier: PHY_TERM_X_R_T_REFCLK_INPUT_OHM)
PHY DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the FPGA DFE.

Legal values are: 0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31.

Note: Refer to Table 170 in the PHY DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_1)
PHY DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the FPGA DFE.

Legal values are: p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8.

Note: Refer to Table 170 in the PHY DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_2)
PHY DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the FPGA DFE.

Legal values are: p7, p6, p5, p4, p3, p2, p1, 0, n, n2, n3, n4, n5, n6, n7, n8.

Note: Refer to Table 170 in the PHY DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_3)
PHY DFE Tap 4

This parameter allows you to select the amount of bias used on tap 3 of the FPGA DFE.

Legal values are: p3, p2, p1, 0, n1, n2, n3, n4.

Note: Refer to Table 170 in the PHY DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: PHY_DFE_X_TAP_4)
Target Write Termination

Specifies the target termination to be used during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_TGT_WR)
Non-Target Write Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_NON_TGT_WR)
Non-Target Read Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a read. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_NON_TGT_RD)
DQ Idle Termination

Specifies the termination to be used for RTT_PARK and DQS_RTT_PARK. For power savings it is recommended to leave this as disabled. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are: off, 1, 2, 3, 4, 5, 6, 7

(Identifier: MEM_ODT_DQ_X_IDLE)
Memory DQ Drive Strength

Specifies the termination to be used when driving read data from memory.

Legal values are: 7, 6, 5

(Identifier: MEM_ODT_DQ_X_RON)
VrefDQ Value

Specifies the initial VrefDQ value to be used.

Legal values are: from 35.00 to 97.50

(Identifier: MEM_VREF_DQ_X_VALUE)
CA Termination

Specifies the termination to be used for the CA bus. This setting only applies to Group B, Group A will always be unterminated. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: off, 0p5, 1, 2, 3, 4, 6

(Identifier: MEM_ODT_CA_X_CA)
CS Termination

Specifies the termination to be used for the CS bus. This setting only applies to Group B, Group A will always be unterminated. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: off, 0p5, 1, 2, 3, 4, 6

(Identifier: MEM_ODT_CA_X_CS)
CK Termination

Specifies the termination to be used for the CK bus. This setting only applies to Group B, Group A will always be unterminated. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are: off, 0p5, 1, 2, 3, 4, 6

(Identifier: MEM_ODT_CA_X_CK)
VrefCA Value

Specifies the initial VrefCA value to be used.

Legal values are: from 35.00 to 97.50

(Identifier: MEM_VREF_CA_X_CA_VALUE)
VrefCS Value

Specifies the initial VrefCS value to be used.

Legal values are: from 35.00 to 97.50

(Identifier: MEM_VREF_CA_X_CS_VALUE)
MEM DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the memory DFE.

Legal values are: p10, p9, p8, p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40.

Note: Refer to Table 171 in the MEM DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: MEM_DFE_X_TAP_1)
MEM DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the memory DFE.

Legal values are: p15, p14, p13, p12, p11, p10, p9, p8, p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15.

Note: Refer to Table 171 in the MEM DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: MEM_DFE_X_TAP_2)
MEM DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the memory DFE.

Legal values are: p12, p11, p10, p9, p8, p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12.

Note: Refer to Table 171 in the MEM DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: MEM_DFE_X_TAP_3)
MEM DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the memory DFE.

Legal values are: p9, p8, p7, p6, p5, p4, p3, p2, p1, 0, n1, n2, n3, n4, n5, n6, n7, n8, n9.

Note: Refer to Table 171 in the MEM DFE Tap Bias Values for DDR5 topic for actual bias values.

(Identifier: MEM_DFE_X_TAP_4)
Table 155.  Group: Example Design / Fileset Types
Parameter Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

Default value is VERILOG

Legal values are: VERILOG, VHDL

(Identifier: EX_DESIGN_HDL_FORMAT)
Generate Synthesis Fileset

Generate Synthesis Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SYNTH)
Generate Simulation Fileset

Generate Simulation Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SIM)
Table 156.  Group: Example Design / User PLL
Parameter Name Description
Auto-set User PLL Output Clock Frequency

if true, let IP select a reference clock frequency for the user PLL in the example design; if false, let user set a custom value for this parameter.

Default value is true

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN)
User PLL Output Clock Frequency

Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode).

Default value is 570

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ)
User PLL Reference Clock Frequency

PLL reference clock frequency in MHz for PLL supplying the core clock.

Default value is 100

(Identifier: EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ)
NOC Reference Clock Frequency

Reference Clock Frequency for the NOC control IP.

Default value is 100

Legal values are: 25, 100, 125

(Identifier: EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ)
Table 157.  Group: Example Design / Traffic Generator
Parameter Name Description
Traffic Generator Remote Access

Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled.

Default value is JTAG

Legal values are: EXPORT, JTAG

(Identifier: EX_DESIGN_TG_CSR_ACCESS_MODE)
Traffic Generator Program

Specifies the traffic pattern to be run.

Default value is MEDIUM

Legal values are: SHORT, MEDIUM, LONG, INFINITE

(Identifier: EX_DESIGN_TG_PROGRAM)
Table 158.  Group: Example Design / Performance Monitor
Parameter Name Description
Enable Performance Monitor for Channel 0

If true, example design will include a Performance Monitor instance connected to Channel 0.

Default value is false

(Identifier: EX_DESIGN_PMON_CH0_EN)
Enable Performance Monitor for Channel 1

If true, example design will include a Performance Monitor instance connected to Channel 1.

Default value is false

(Identifier: EX_DESIGN_PMON_CH1_EN)
Level Two Title