GTS CPRI PHY Intel® FPGA IP User Guide

Download PDF
ID 814577
Date 3/31/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generating File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath and PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.8. Status Interface for 8b/10b Line Rate

This section lists the status ports for the CPRI PHY 8b/10b line rate. Each CPRI PHY channel has its own status port.
Table 22.  CPRI PHY Status Interface Signals for 8b/10b Interface
Port Name Width (Bits) Domain Description
o_rx_patterndetect 1 o_rx_clkout2 The IP core asserts this signal to indicate that K28.5 has been detected in the current word boundary of o_rx_d or o_rx_c and the received data from the RX PMA achieved the word alignment.

This interface should be observed in conjunction with o_rx_disperr and i_rx_errdetect.

o_rx_disperr[1:0] 2 o_rx_clkout2 The IP core asserts this signal to indicate that the IP received 10-bit code or data group in the current word boundary of o_rx_d or o_rx_c has a disparity error.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.
o_rx_errdetect[1:0] 2 o_rx_clkout2 The IP core asserts this signal to indicate that it received 10-bit data group in the o_rx_d or o_rx_c has an 8b/10b code violation.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.
Level Two Title