Visible to Intel only — GUID: ohd1684441924954
Ixiasoft
Visible to Intel only — GUID: ohd1684441924954
Ixiasoft
5.3.6.10. Controller Fixed Parameters and Clock Frequencies Supported
This section provides configuration parameters for which the NAND Controller has been pre-configured. This includes overall parameters in the NAND controller and some internal components.
Parameter | Value |
---|---|
Master and Slave Data Port Address Bus Width | AXI4 64 bits |
Master and Slave Data Port Data Bus Width | AXI4 64 bits |
Maximum Page Size in Flash Device | 64 KB |
Context Storage RAM - SPRAM | 64bits x 80 words = 5120 bits |
Records Table storage RAM - SPRAM | 68 bits x 1024 words = 69632 bits |
TX FIFO RAM - DPRAM | (64 data bits + 8 parity) x 128 words = 9216 |
nf_clk Clock | This clock drives the mini controller and PHY modules. Min: 20 MHz Max: 400MHz. |
bch_clk Clock22 | This clock drives the controller's BCH engine. The bch_clk frequency depends on the BCH configuration and should be trimmed depending on the BCH engine paralleling factors and the nf_clk clock frequency value. Min: 20 MHz Max: 400MHz |
sys_clk Clock22 | This clock drives most of the controller logic except ECC, the minicontroller, and SFR interface modules. Its frequency should match the host interface clock frequency. Min: 20 MHz Max: 400MHz |
sfr_clk Clock22 | This clock drives the controller’s slave register port. It allows the register interface to operate at lower speed. Min: 1 MHz Max: 400MHz (must be lower than or equal to sys_clk) |
dphy_reg_clk Clock22 | This clock drives the controller’s PHY register port. It allows the controller and PHY register interfaces to operate at lower speed. Min: 20 MHz Max: 400MHz |
NAND Controller Reset | The NAND Flash controller receives a single nand_flash_rst_n signal from the reset manager. |