GTS JESD204C Intel® FPGA IP Design Example User Guide

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ID 813978
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

2.6. Compiling and Testing the Design

The GTS JESD204C Intel® FPGA IP parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Quartus® Prime software and compile the design (Processing > Start Compilation). The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
    Table 7.  Clock Settings
    Clock Name Clock Frequency
    refclk_xcvr Select the frequency for the transceiver PLL reference clock in the IP parameter editor.
    refclk_core Select the frequency for the core PLL reference clock in the IP parameter editor.
    mgmt_clk 100 MHz
    Figure 7. Clock Control GUI SettingsThe following example shows the clock control GUI settings for a design example running at 15.6025 Gbps.
  3. If you are performing external loopback test, attach the QSFP-DD loopback module at cage (U12).
  4. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
    To run the hardware testing using the Tcl script, refer to the Hardware Test for System Console Control Design Example section.
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