GTS JESD204C Intel® FPGA IP Design Example User Guide

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ID 813978
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

2.4. Dual Simplex Design Example

Figure 4. Dual Simplex Design Example Block Diagram

The Dual Simplex example design currently supports Duplex Case only with TX and RX in the same configuration. For more information, refer to the Dual Simplex Support section in the GTS JESD204C Intel® FPGA IP User Guide.

To generate the design example:

  1. Create a project targeting Agilex™ 5 device family and select the desired device.
  2. In the IP Catalog, Tools > IP Catalog, select GTS JESD204C Intel® FPGA IP . Modify the IP Tab for required JESD configurations. Current JESD IP supports same configuration for both TX and RX.
  3. In the GTS JESD204C Intel® FPGA IP GUI, go to the Example Design tab and enable Enable dual simplex generation.
  4. Generate the example design and after opening the example design, choose the Dual Simplex assignment editor in the Assignments menu.
  5. Verify the TX and RX PHY relative offsets. Save assignments and run IP generation in Quartus® Prime. This will generate the HSSI dual simplex generation.
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