GTS JESD204C Intel® FPGA IP Design Example User Guide

Download PDF
ID 813978
Date 7/12/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

2.3. Generating the Design

To generate the design example from the IP parameter editor:

  1. Create a project targeting Agilex™ 5 device family and select the desired device.
  2. In the IP Catalog, Tools > IP Catalog, select GTS JESD204C Intel® FPGA IP .
  3. Specify a top-level name and the folder for your custom IP variation. This name identifies the IP variation files in your project. If prompted, also specify the target Intel FPGA device family and output file HDL preference. Click OK. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/ Remove Files in Project to add the file.
  4. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
  5. Click Generate Example Design.
The software generates all design files in the sub-directories. These files are required to run simulation and compilation.

Section Content
Design Example Parameters
Directory Structure

Level Two Title