GTS JESD204C Intel® FPGA IP Design Example User Guide

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ID 813978
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

2.3.1. Design Example Parameters

The GTS JESD204C Intel® FPGA IP parameter editor includes the Example Design tab for you to specify certain parameters before generating the design example.
Table 5.  Parameters in the Example Design Tab
Parameter Options Description
Select Design
  • System Console Control
  • None
 Select the system console control to access the design example data path through the system console.
Simulation On, Off Turn on for the IP to generate the necessary files for simulating the design example.
Synthesis On, Off Turn on for the IP to generate the necessary files for Quartus® Prime compilation and hardware demonstration.
HDL format (for simulation)
  • Verilog
  • VDHL
 Select the HDL format of the RTL files for simulation.
HDL format (for synthesis) Verilog only Select the HDL format of the RTL files for synthesis.
Generate 3-wire SPI module On, Off

Turn on to enable 3-wire SPI interface instead of 4-wire.

Sysref mode
  • One-shot
  • Periodic
  • Gapped periodic

Select whether you want the SYSREF alignment to be a one-shot pulse mode, periodic, or gapped periodic, based on your design requirements and timing flexibility.

  • One-shot—Select this option to enable SYSREF to be a one-shot pulse mode. The sysref_ctrl[17] register bit's value is 0. After the GTS JESD204C IP reset deasserts, change the sysref_ctrl[17] register's value from 0 to 1, then to 0, for a one-shot SYSREF pulse.
  • Periodic—SYSREF in periodic mode has 50:50 duty cycle. SYSREF period is E*SYSREF_MULP.
  • Gapped periodic—SYSREF has programmable duty cycle of granularity of 1 link clock cycle. SYSREF period is E*SYSREF_MULP. For out-of-range duty cycle setting, the SYSREF generation block should automatically infer 50:50 duty cycle.
Refer to the SYSREF Generator section for more information about the SYSREF period.
Note: Sysref mode is for internal SYSREF generator use only.
Test Pattern
  • PRBS-7
  • PRBS-9
  • PRBS-15
  • PRBS-23
  • Ramp
 Select pattern generator and checker test pattern.
  • Pattern Generator—JESD204C support PRBS pattern generator per data sample. This means that the width of the data is N+CS option. PRBS pattern generator and checker are useful for creating data sample stimulus for testing and it is not compatible with PRBS test mode on the ADC/DAC converter.
  • Ramp Pattern Generator—JESD204C link layer operates normally but the transport later is disabled and the input from the formatter is ignored. Each lane transmits an identical octet stream that increments from 0x00 to 0xFF and then repeats. Ramp pattern test is enable by prbs_test_ctl.
  • PRBS Pattern Checker—JESD204C PRBS scrambler is self synchronizing and it is expected that when the IP core is able to decode link up, the scrambling seed is already synchronized. PRBS scrambling seed will take up 8 octets to self initialize.
  • Ramp Pattern Checker—JESD204C scrambling is self synchronizing and it is expected that when the IP core is able to decode link up, the scrambling seed is already synchronized. The first valid octet is loaded as the ramp initial value. Subsequent data must increment up to 0xFF and roll over to 0x00. Ramp pattern checker should check for identical pattern across all lanes.
Enable Command Channel On, Off Select command channel pattern.
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