GTS JESD204C Intel® FPGA IP Design Example User Guide

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ID 813978
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

3.2. GTS JESD204C Design Example Clock and Reset

The GTS JESD204C design example has a set of clock and reset signals.
Table 12.  Design Example Clocks
Clock Signal Direction Description
mgmt_clk Input LVDS differential clock with frequency of 100 MHz.
refclk_xcvr Input Transceiver reference clock with frequency of the PLL Selection.
refclk_core Input Core reference clock with the same frequency as refclk_xcvr.
in_sysref Input SYSREF signal.

Maximum SYSREF frequency is data rate/(66x32xE).

sysref_out Output

txlink_clk

rxlink_clk

Internal TX and RX link clock with frequency of data rate/66.

txframe_clk

rxframe_clk

Internal
  • TX and RX frame clock with frequency of data rate/33 (FCLK_MULP=2)
  • TX and RX frame clock with frequency of data rate/66 (FCLK_MULP=1)

tx_fclk

rx_fclk

Internal
  • TX and RX phase clock with frequency of data rate/66 (FCLK_MULP=2)
  • TX and RX phase clock is always high (1'b1) when FCLK_MULP=1
spi_SCLK Output SPI baud rate clock with frequency of 20 MHz.
pma_cu_clk Internal The internal clock from the GTS Reset Sequencer Intel® FPGA IP to the transceiver logic.

When you load the design example into an FPGA device, an internal ninit_done event ensures that the JTAG to Avalon® Master bridge is in reset as well as all the other blocks.

The SYSREF generator has its independent reset to inject intentional asynchronous relationship for the txlink_clk and rxlink_clk clocks. This method is more comprehensive in emulating the SYSREF signal from an external clock chip.

Table 13.  Design Example Resets
Reset Signal Direction Description
global_rst_n Input Push button global reset for all blocks, except the JTAG to Avalon® Master bridge.
ninit_done Internal Output from Reset Release IP for the JTAG to Avalon® Master bridge.
edctl_rst_n Internal The ED Control block is reset by JTAG to Avalon® Master bridge. The hw_rst and global_rst_n ports do not reset the ED Control block.
hw_rst Internal Assert and deassert hw_rst by writing to the rst_ctl register of the ED Control block. mgmt_rst_in_n asserts when hw_rst is asserted.
mgmt_rst_in_n Internal Reset for Avalon® memory-mapped interfaces of various IPs and inputs of reset sequencers:
  • reconfig_xcvr_reset for GTS JESD204C IP duplex Native PHY
  • spi_rst_n for SPI master
  • pio_rst_n for PIO status and control
  • reset_in0 port of reset sequencer 0 and 1

The global_rst_n, hw_rst, or edctl_rst_n port asserts reset on mgmt_rst_in_n.

sysref_rst_n Internal Reset for SYSREF generator block in the ED Control block using the reset sequencer 0 reset_out2 port. The reset sequencer 0 reset_out2 port deasserts the reset if the core PLL is locked.
core_pll_rst Internal Resets the core PLL through the reset sequencer 0 reset_out0 port. The core PLL resets when mgmt_rst_in_n reset is asserted.
j204c_tx_avs_rst_n Internal Resets the GTS JESD204C TX Avalon® memory-mapped interface through reset sequencer 0. The TX Avalon® memory-mapped interface asserts when mgmt_rst_in_n is asserted.
j204c_rx_avs_rst_n Internal Resets the GTS JESD204C TX Avalon® memory-mapped interface through reset sequencer 1. The RX Avalon® memory-mapped interface asserts when mgmt_rst_in_n is asserted.
j204c_tx_rst_n Internal Resets the GTS JESD204C TX link and transport layers in txlink_clk, and txframe_clk, domains.

The reset sequencer 0 reset_out5 port resets j204c_tx_rst_n. This reset deasserts if the core PLL is locked, and the j204c_tx_rst_ack_n signal is asserted.

j204c_rx_rst_n Internal Resets the GTS JESD204C RX link and transport layers in, rxlink_clk,and rxframe_clk domains.

The reset sequencer 1 reset_out4 port resets j204c_rx_rst_n. This reset deasserts if the core PLL is locked, and the j204c_rx_rst_ack_n signal is asserted.

j204c_tx_rst_ack_n Internal Reset handshakes signal with j204c_tx_rst_n.
j204c_rx_rst_ack_n Internal Reset handshakes signal with j204c_rx_rst_n.
Figure 8. Timing Diagram for the Design Example Resets
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