GTS Serial Lite IV Intel® FPGA IP User Guide

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ID 813966
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series Devices 2. GTS Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. GTS Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with GTS Serial Lite IV Intel® FPGA IP 8. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP User Guide
2. GTS Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. GTS Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. GTS Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA/PCS Signals
7. Designing with GTS Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. Analog Parameter Settings
1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series Devices
2. GTS Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. GTS Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with GTS Serial Lite IV Intel® FPGA IP
8. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP User Guide

2. GTS Serial Lite IV Intel® FPGA IP Overview

GTS Serial Lite IV Intel® FPGA IP is suitable for high bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.

The GTS Serial Lite IV Intel® FPGA IP incorporates media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) blocks.

The IP supports data transfer speeds of:.
  • Up to 16 Gbps per lane with a maximum of 4 lane for NRZ mode GTS transceiver.

This IP offers high bandwidth, low overhead frames, low I/O count, and supports high scalability in both numbers of lanes and speed. This IP is also easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the transceiver.

This IP supports two transmission modes:
  • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
  • Full mode—This is a packet transfer mode. In this mode, the IP sends a burst and a sync cycle at the start and end of a packet as delimiters.
Figure 1.  GTS Serial Lite IV High Level Block Diagram

You can generate GTS Serial Lite IV Intel® FPGA IP design examples to learn more about the IP features.


Section Content
Release Information
Supported Features
IP Version Support Level
Device Speed Grade Support
Resource Utilization and Latency
Bandwidth Efficiency

Related Information
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