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1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO Intel® FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused HSIO Banks
2.5.14. HSIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for HSIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
7.1. Release Information for GPIO Intel® FPGA IP
7.2. Generating the GPIO Intel® FPGA IP
7.3. GPIO Intel® FPGA IP Parameter Settings
7.4. GPIO Intel® FPGA IP Interface Signals
7.5. GPIO Intel® FPGA IP Architecture
7.6. Verifying Resource Utilization and Design Performance
7.7. GPIO Intel® FPGA IP Timing
7.8. GPIO Intel® FPGA IP Design Examples
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2.5.14. HSIO Pins During Power Sequencing
Agilex™ 5 devices do not support hot-socketing and require a specific power sequence. Design your power supply solution to properly control the complete power sequence.
Adhere to the these guidelines to prevent unnecessary current draw on the I/O pins located in the HSIO banks. These guidelines apply for unpowered, power up to power-on reset (POR), POR delay, POR delay to configuration, configuration, initialization, user mode, and power down device states.
- The I/O pins in the HSIO banks can be tri-stated, driven to ground, or driven to the VCCIO_PIO level.
- While the device is powering up or down:
- The input signals of an I/O pin, at all times, must not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.
- If you use a pin in a HSIO bank with 1.3 V VCCIO_PIO, the pin voltage must not exceed the VCCIO_PIO rail or 1.2 V, whichever is lower.
- While the device is powering up or powering down, the HSIO pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per HSIO bank.
- While the device is not turned on, tri-state the I/O pin and do not drive the pin with any external voltage.
- After the device fully powers up, the voltage levels for the HSIO pins must not exceed the DC input voltage (VI) value or the AC maximum allowed overshoot during transitions.
Condition | Guideline |
---|---|
The VCCIO_PIO pin ramps up and at period X, the VCCIO_PIO voltage is 1.1 V. | At period X, keep the signals driven by the device connected to the HSIO I/O pin at a voltage of 1.1 V or lower. |
The 1.3 V VCCIO_PIO pin ramps up and the voltage continues to rise pass the 1.2 V level. | Keep the HSIO pin voltage at 1.2 V or lower until the device fully powers up. |