General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

7.5.1.1. Input Path

The pad sends data to the input buffer, and the input buffer feeds the delay element. After the data goes to the output of the delay element, the programmable bypass multiplexers select the features and paths to use.
Figure 39. Simplified View of Single-Ended HSIO Input Path


Figure 40. Input Path Waveform in DDIO ModeThe actual timing relationship between different signals may vary depending on the specific design, delays, and phases that you specify for the clock.