General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

2.5.20. Implementing a Pseudo Open Drain

Apply this method to implement a pseudo open drain for Agilex™ 5 devices using the LVCMOS I/O standard.
Figure 25. Pseudo Open Drain Connection


  1. Use the GPIO IP to initiate an output or bidirectional buffer with the OE turned on.
  2. Connect the input port of the output buffer to the ground.
  3. Connect the actual data signal to the OE port.
Note: Drive the buffer LOW before you switch the OE signal. When you switch the OE signal to HIGH, the output pin drives LOW. When you switch the OE signal to LOW, the output pin is tri-stated. You need an external pull-up circuitry to pull the connection to HIGH.