General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

2.2.1. Supported I/O Standards for HSIO Banks

The VCCIO_PIO and VCCPT power supplies power the HSIO buffers. Each I/O sub-bank has its own VCCIO_PIO power supply and supports only one I/O voltage.

The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL standards at a lower signal swing.

You can place the True Differential Signaling input buffer in a HSIO bank powered by 1.05 V, 1.1 V, 1.2 V and 1.3 V VCCIO_PIO. The maximum input voltage to the True Differential Signaling input buffer must not exceed the value of :
  • For 1.05 V, 1.1 V, and 1.2 V VCCIO_PIO, the maximum input voltage is 1.177 V
  • For 1.3 V VCCIO_PIO bank, the maximum input voltage depends on the termination:
    • On-chip differential termination (RD OCT) enabled—maximum input voltage is 1.602 V
    • On-board differential termination with RD OCT disabled—maximum input voltage is 1.427 V with VICM capped at 1.2 V

By default, the Quartus® Prime software assigns 1.2 V to the VCCIO_PIO pin in unused I/O sub-banks.

Table 2.   HSIO Bank Supported I/O StandardsThis table lists the input and output voltages of a HSIO bank.
I/O Standard VCCIO_PIO (V) VCCPT (V) JEDEC Standard
Input Output
1.3 V LVCMOS 1.3 1.3 1.8
1.2 V LVCMOS 1.2 1.2 1.8 JESD8-12A.01
1.1 V LVCMOS 1.1 1.1 1.8
1.05 V LVCMOS 1.05 1.05 1.8
1.0 V LVCMOS 1.0 1.0 1.8
SSTL-12 2 1.2 1.2 1.8 JESD79-4B
HSTL-12 2 1.2 1.2 1.8 JESD-16A
HSUL-12 2 1.2 1.2 1.8 JESD209-3C
POD12 2 1.2 1.2 1.8 JESD79-4B
POD11 2 1.1 1.1 1.8 JESD79-5
LVSTL11 1.1 1.1 1.8 JESD209-4C
LVSTL105 1.05 1.05 1.8 JESD209-5
LVSTL700 3 1.05 1.05 1.8

JESD209-4-1

JESD209-5

Differential SSTL-12 2 4 1.2 1.2 1.8 JESD79-4B
Differential HSTL-12 2 4 1.2 1.2 1.8 JESD8-16A
Differential HSUL-12 2 4 1.2 1.2 1.8 JESD209-3C
Differential POD-12 2 4 1.2 1.2 1.8 JESD79-4B
Differential POD11 2 4 1.1 1.1 1.8 JESD79-5
Differential LVSTL11 4 1.1 1.1 1.8 JESD209-4C
Differential LVSTL105 4 1.05 1.05 1.8 JESD209-5
Differential LVSTL700 3 4 1.05 1.05 1.8

JESD209-4-1

JESD209-5

SLVS-400 3 1.1/1.2 1.1/1.2 1.8 JESD8-13
DPHY 3 1.1/1.2 1.1/1.2 1.8
True Differential Signaling 2 1.05/1.1/1.2/1.3 1.3 1.8
2 Input buffers are powered by 1.8 V VCCPT
3 Not supported in GPIO mode.
4 Uses two single-ended outputs with second output programmed as inverted.