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1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO Intel® FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused HSIO Banks
2.5.14. HSIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for HSIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
7.1. Release Information for GPIO Intel® FPGA IP
7.2. Generating the GPIO Intel® FPGA IP
7.3. GPIO Intel® FPGA IP Parameter Settings
7.4. GPIO Intel® FPGA IP Interface Signals
7.5. GPIO Intel® FPGA IP Architecture
7.6. Verifying Resource Utilization and Design Performance
7.7. GPIO Intel® FPGA IP Timing
7.8. GPIO Intel® FPGA IP Design Examples
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2.2.1. Supported I/O Standards for HSIO Banks
The VCCIO_PIO and VCCPT power supplies power the HSIO buffers. Each I/O sub-bank has its own VCCIO_PIO power supply and supports only one I/O voltage.
The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL standards at a lower signal swing.
You can place the True Differential Signaling input buffer in a HSIO bank powered by 1.05 V, 1.1 V, 1.2 V and 1.3 V VCCIO_PIO. The maximum input voltage to the True Differential Signaling input buffer must not exceed the value of :
- For 1.05 V, 1.1 V, and 1.2 V VCCIO_PIO, the maximum input voltage is 1.177 V
- For 1.3 V VCCIO_PIO bank, the maximum input voltage depends on the termination:
- On-chip differential termination (RD OCT) enabled—maximum input voltage is 1.602 V
- On-board differential termination with RD OCT disabled—maximum input voltage is 1.427 V with VICM capped at 1.2 V
By default, the Quartus® Prime software assigns 1.2 V to the VCCIO_PIO pin in unused I/O sub-banks.
I/O Standard | VCCIO_PIO (V) | VCCPT (V) | JEDEC Standard | |
---|---|---|---|---|
Input | Output | |||
1.3 V LVCMOS | 1.3 | 1.3 | 1.8 | — |
1.2 V LVCMOS | 1.2 | 1.2 | 1.8 | JESD8-12A.01 |
1.1 V LVCMOS | 1.1 | 1.1 | 1.8 | — |
1.05 V LVCMOS | 1.05 | 1.05 | 1.8 | — |
1.0 V LVCMOS | 1.0 | 1.0 | 1.8 | — |
SSTL-12 2 | 1.2 | 1.2 | 1.8 | JESD79-4B |
HSTL-12 2 | 1.2 | 1.2 | 1.8 | JESD-16A |
HSUL-12 2 | 1.2 | 1.2 | 1.8 | JESD209-3C |
POD12 2 | 1.2 | 1.2 | 1.8 | JESD79-4B |
POD11 2 | 1.1 | 1.1 | 1.8 | JESD79-5 |
LVSTL11 | 1.1 | 1.1 | 1.8 | JESD209-4C |
LVSTL105 | 1.05 | 1.05 | 1.8 | JESD209-5 |
LVSTL700 3 | 1.05 | 1.05 | 1.8 | JESD209-4-1 JESD209-5 |
Differential SSTL-12 2 4 | 1.2 | 1.2 | 1.8 | JESD79-4B |
Differential HSTL-12 2 4 | 1.2 | 1.2 | 1.8 | JESD8-16A |
Differential HSUL-12 2 4 | 1.2 | 1.2 | 1.8 | JESD209-3C |
Differential POD-12 2 4 | 1.2 | 1.2 | 1.8 | JESD79-4B |
Differential POD11 2 4 | 1.1 | 1.1 | 1.8 | JESD79-5 |
Differential LVSTL11 4 | 1.1 | 1.1 | 1.8 | JESD209-4C |
Differential LVSTL105 4 | 1.05 | 1.05 | 1.8 | JESD209-5 |
Differential LVSTL700 3 4 | 1.05 | 1.05 | 1.8 | JESD209-4-1 JESD209-5 |
SLVS-400 3 | 1.1/1.2 | 1.1/1.2 | 1.8 | JESD8-13 |
DPHY 3 | 1.1/1.2 | 1.1/1.2 | 1.8 | — |
True Differential Signaling 2 | 1.05/1.1/1.2/1.3 | 1.3 | 1.8 | — |
2 Input buffers are powered by 1.8 V VCCPT
3 Not supported in GPIO mode.
4 Uses two single-ended outputs with second output programmed as inverted.