General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public
Document Table of Contents

2.2.2. HSIO Buffer Behavior

Table 3.   HSIO Pins Guideline for Different Pin States
HSIO Pin State
Not turned on Powering up Fully powered up Configuration mode User mode Powering down

Either tri-state the pins or do not drive them with any external voltage.

  • Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.
  • After full VCCIO_PIO power up, the pins are tri-stated with weak pull-up enabled.

All pins are tri-stated with weak pull-up enabled.

All pins are tri-stated with weak pull-up enabled.

Valid data transactions can be initiated.

  • Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.
  • When the VCCIO_PIO and VCC power rails are powering down, the I/O pin signals measure between ground and the VCCIO_PIO voltage levels.
Note: After the Agilex™ 5 device fully powers up, the voltage levels for the HSIO pins must not exceed the DC input voltage (VI) value or the AC maximum allowed overshoot during transitions.