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1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO Intel® FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused HSIO Banks
2.5.14. HSIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for HSIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
7.1. Release Information for GPIO Intel® FPGA IP
7.2. Generating the GPIO Intel® FPGA IP
7.3. GPIO Intel® FPGA IP Parameter Settings
7.4. GPIO Intel® FPGA IP Interface Signals
7.5. GPIO Intel® FPGA IP Architecture
7.6. Verifying Resource Utilization and Design Performance
7.7. GPIO Intel® FPGA IP Timing
7.8. GPIO Intel® FPGA IP Design Examples
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7.7.2. Delay Elements
The Quartus® Prime software does not automatically set delay elements to maximize slack in the I/O timing analysis. To close the timing or maximize slack, set the delay elements manually in the Quartus® Prime settings file (.qsf).
Delay Element | .qsf Assignment |
---|---|
Input Delay Element | set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63> |
Output Delay Element | set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15> |
Output Enable Delay Element | set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15> |