Visible to Intel only — GUID: bej1697043581944
Ixiasoft
Visible to Intel only — GUID: bej1697043581944
Ixiasoft
7.2.1. Interface Clock Signals
Signal Name | Direction | Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) | Description |
---|---|---|---|
refclk0 refclk1 |
Input | EP/RP/BP | These are the input reference clocks for the IP core to drive the TX PLL and CDR in PMA. The Source from the PCIe* link or local oscillator depending on the PCIe* link clock topology. Frequency = 100 MHz ± 300 ppm For systems that do not employ spread spectrum clocking, or use common clock source. |
i_syspll_c0_clk | Input | EP/RP/BP | This clock is driven from a System PLL located in the same GTS transceiver bank as the PCIe* lanes. |
i_ss_vccl_syspll_locked | Input | EP/RP/BP | Indicates the System PLL locks to reference clock. The System PLL needs to achieve lock before cold or warm reset take place. Must be connected to the output o_pll_lock signal of GTS System PLL Clocks Intel® FPGA IP. |
p0_axi_st_clk p1_axi_st_clk |
Input | EP/RP/BP | Global clock signal for AXI-Stream interface. All AXI-Stream signals are sampled on the rising edge of this clock. This clock drives the main data path. The clock frequency follows the PLD clock frequency setting in the GTS AXI Streaming IP. Refer to the Clock Domains in GTS AXI Streaming IP table for more information about the frequency. |
p0_axi_lite_clk p1_axi_lite_clk |
Input | EP/RP/BP | The global clock signal for AXI-Lite interface. All AXI-Lite signals are sampled on the rising edge of this clock. This clock drives the AXI4-Lite Control and Status Register Responder interface. Frequency: 100–250 MHz |
coreclkput_hip_toapp | Output | EP/RP/BP | The coreclkout_hip output of HIP drives this clock. Use this clock to drive p0_axi_st_clk, p1_axi_st_clock. PCIe* 4.0: 500/450/400/350/300/250/200 MHz (x8) PCIe* 4.0: 350/300/250/200 MHz (x4) PCIe* 4.0: 300/250/200 MHz (x2, x1) PCIe* 3.0: 350/300/250/200 (x8) PCIe* 3.0: 300/250/200 MHz (x4, x2, x1) The coreclkout_hip_toapp clock frequency depends on the PLD Clock Frequency you choose in the IP parameter editor. |
i_flux_clk i_flux_clk_1 |
Input | EP/RP/BP | Must be connected to the output o_pma_cu_clk of the GTS Reset Sequencer Intel® FPGA IP. i_flux_clk_1 is only available in x8 mode in the Agilex™ 5 D-Series FPGAs. |