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1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters for E-Series FPGA
6. IP Parameters for D-Series FPGAs
7. Interfaces and Signals
8. Registers
9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP
3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Precision Time Measurement (PTM)
4.11. Single Root I/O Virtualization (SR-IOV)
4.12. Transaction Layer Packet (TLP) Bypass Mode
4.13. Scalable IOV
7.1. Overview
7.2. Clocks and Resets
7.3. AXI4-Stream Interfaces
7.4. Configuration Intercept Interface
7.5. Control Shadow Interface
7.6. Transmit Flow Control Credit Interface
7.7. Completion Timeout Interface
7.8. Control and Status Register Responder Interface
7.9. Function Level Reset Interface
7.10. TLP Bypass Error Reporting Interface
7.11. VF Error Flag Interface
7.12. Precision Time Measurement (PTM) Interface
7.13. Serial Data Signals
7.14. Miscellaneous Signals
8.6.1. VF PCI-Compatible Configuration Space Header Type0
8.6.2. VF PCI Express* Capability Structure
8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
8.6.4. VF Alternative Routing ID (ARI) Capability Structure
8.6.5. VF TLP Processing Hints (TPH) Capability Structure
8.6.6. VF Address Translation Services (ATS) Capability Structure
8.6.7. VF Access Control Services (ACS) Capability Structure
8.6.2.1. PCI Express* Capability List Register
8.6.2.2. PCI Express* Device Capabilities Register
8.6.2.3. PCI Express* Device Control and Status Register
8.6.2.4. Link Capabilities Register
8.6.2.5. Link Control and Status Register
8.6.2.6. PCI Express* Device Capabilities 2 Register
8.6.2.7. PCI Express* Device Control and Status 2 Register
8.6.2.8. Link Capabilities 2 Register
8.6.2.9. Link Control and Status 2 Register
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3.2. Configuring and Generating the GTS AXI Streaming IP
Adhere to the following procedure to generate the GTS AXI Streaming IP in standalone mode.
- Use the Quartus® Prime Pro Edition software to create a Quartus Project and select the required device. Currently, only Agilex™ 5 (E-Series) device supports the GTS AXI Streaming IP (for example, A5ED065BB32AE5SR0).
- The GTS AXI Streaming Intel® FPGA IP for PCI Express* parameter editor allows you to quickly configure your custom IP variation. Invoke the IP parameter editor using the following steps to specify IP core options and parameters in the Quartus® Prime Pro Edition software.
- Select GTS AXI Streaming Intel® FPGA IP for PCI Express* in the IP Catalog.
- A New IP Variant window appears. Specify a top-level name for your new custom IP variation. The IP parameter editor saves the IP variation settings in a file named <your_ip>.ip.
- Click Create. The IP parameter editor appears.
- Specify the parameters for your IP core variation. For information about specific IP core parameters, refer to the IP Parameter section.
- Generate the GTS AXI Streaming Intel® FPGA IP for PCI Express* .
- Click Generate HDL. The Generation dialog box appears. Specify output file generation options.
- Click Generate. This allows you to generate a GTS AXI Streaming IP in the standalone mode with the IP variation files are generated according to your specifications.
- Click Close. The IP parameter editor adds the top-level.ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
- Use the Generate Example Designs box to generate the GTS AXI Streaming IP as part of a Quartus generated dynamic design example which instantiates the GTS AXI Streaming IP with the chosen parameters, along with a basic application and software drivers to run the Programmable Input Output (PIO) type traffic tests.
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