GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

5. IP Parameters

The GTS AXI Steamig IP paamete edito i the Quatus® Pime Po Editio softwae povides the paametes you ca set to cofigue you GTS AXI Steamig IP vaiatio.

System Settigs

Figue 33. Example System Settigs Tab i the GTS AXI Steamig IP Paamete Edito
Table 27.   GTS AXI Steamig IP Paametes: System Settigs Tab
Paamete Value Default Settig Desciptio
System Settigs
PCIe* 0 Had IP Mode
  • Ge4x4 Iteface 256 bit
  • Ge4x2 Iteface 128 bit
  • Ge4x1 Iteface 128 bit
  • Ge3x4 Iteface 128 bit
  • Ge3x2 Iteface 128 bit
  • Ge3x1 Iteface 128 bit
  • Disabled

Ge3 x4 Iteface 128 bit

Selects the width of the data iteface betwee the tasactio laye ad the applicatio laye implemeted i the PLD fabic, the lae data ate, ad the lae ate.

PCIe* 1 Had IP Mode
  • Ge4x8 Iteface 512 bit
  • Ge3x8 Iteface 256 bit
  • Disabled
Disabled Selects the width of the data iteface betwee the tasactio laye ad the applicatio laye implemeted i the PLD fabic, the lae data ate, ad the lae ate. The Ge4x8 ad Ge3x8 optios ae available whe PCIe* 0 Had IP Mode is set to Disabled.
Note: This optio is oly available i the D-Seies FPGAs.
PCIe* 0 Eable TLP-bypass mode
  • Tue
  • False
False

Eables the TLP Bypass featue fo PCIe* 0.

PCIe* 1 Eable TLP-bypass mode
  • Tue
  • False
False
Eables the TLP Bypass featue fo PCIe* 1.
Note: This optio is oly available i the D-Seies FPGAs.
PCIe* 0 Pot Mode
Whe you set Eable TLP-bypass mode to false, the followig values ae available:
  • Root Pot
  • Native Edpoit
Native Edpoit

Selects the pot mode fo PCIe* 0.

Whe you set Eable TLP-bypass mode to tue, the followig values ae available:
  • Dowsteam Pot
  • Upsteam Pot
Upsteam Pot
PCIe* 1 Pot Mode
Whe you set Eable TLP-bypass mode to false, the followig values ae available:
  • Root Pot
  • Native Edpoit
Native Edpoit
Selects the pot mode fo PCIe* 1.
Note: This optio is oly available i the D-Seies FPGAs.
Whe you set Eable TLP-bypass mode to tue, the followig values ae available:
  • Dowsteam Pot
  • Upsteam Pot
Upsteam Pot
PLD Clock Fequecy
  • 500 MHz
  • 450 MHz
  • 400 MHz
  • 350 MHz
  • 300 MHz
  • 250 MHz
  • 200 MHz
300 MHz

Selects the PLD clock fequecy.

Note:
  1. Select the optimum PLD clock fequecy to achieve maximum badwidth. Refe to the Simple Packig Data Width ad Optimum PLD Clock Fequecy table fo moe details o the PLD clock fequecies.
  2. Highe tha the optimum PLD clock fequecy is allowed fo some of the Had IP modes above povided that the timig equiemets ca be met.
Eable SRIS Mode
  • Tue
  • False
False

Eables the Sepaate Refeece Clock with Idepedet Spead Spectum Clockig (SRIS) featue.
Eable PIPE Mode Simulatio
  • Tue
  • False
False

Whe selected, the PIPE mode simulatio is eabled.

Note: This paamete is ot suppoted fo Quatus® Pime compilatio.

The PIPE mode simulatio is ot suppoted fo Questa* Itel® FPGA Editio.

Whe uig simulatios with this paamete eabled, the followig maco is equied with the FASTSIM mode eabled: "+defie+SM_PIPE_MODE"

Eable CVP (Itel VSEC)
  • Tue
  • False
False Eables CvP fo the device.

PCIe0/PCIe1

Itefaces Pot 0/Itefaces Pot 1

Figue 34. Example Itefaces Pot 0/Iteface Pot 1 Settigs Tab i the GTS AXI Steamig IP Paamete Edito
Table 28.   GTS AXI Steamig IP Paametes: Itefaces Pot 0/Itefaces Pot 1 Settigs Tab
Paamete Value Default Value Desciptio
Eable PCIe* 0/ PCIe* 1 Cotol Shadow Iteface
  • Tue
  • False
False

Eables the Cotol Shadow Iteface. Host wite to specific PCIe* cofiguatio space egiste's bit is idicated though this iteface.

Eable PCIe* 0/ PCIe* 1 Completio Timeout Iteface
  • Tue
  • False
False

Eables the Completio Timeout Iteface. Completio Timeout evet is idicated though this iteface.
Eable PCIe* 0/ PCIe* 1 Cofiguatio Extesio Bus Iteface
  • Tue
  • False
False

Eables the Cofiguatio Extesio Bus Iteface. You ca add additioal PCIe* capabilities usig this iteface.

Whe you set Eable PCIe* 0/ PCIe* 1 Cofiguatio Extesio Bus Iteface to Tue, the followig optios ae available:

PCIe 0/PCIe1 Stadad ext addess poite fo PF 0x000 to 0x03F 0x00000000 Eable CEB poite addess fo PF (DW addess i hex).
PCIe 0/PCIe1 Exteded ext addess poite fo PF 0x040 to 0x3FF 0x00000000 Eable CEB poite addess fo PF (DW addess i hex).
PCIe 0/PCIe1 Stadad ext addess poite fo VF 0x000 to 0x03F 0x00000000 Eable CEB poite addess fo VF (DW addess i hex).
PCIe 0/PCIe1 Exteded ext addess poite fo VF 0x040 to 0x3FF 0x00000000 Eable CEB poite addess fo VF (DW addess i hex).
PCIe 0/PCIe1 CEB REQ to ACK Latecy Timeout value 1-256 100 Eable CEB REQ to ACK Latecy Timeout value (i clock cycles).
Eable PCIe0/Cofiguatio Itecept Iteface
  • Tue
  • False
False Eables the Cofiguatio Itecept Iteface. You ca itecept PCIe* cofiguatio cycles usig this iteface.
Whe you set Eable PCIe0/Cofiguatio Itecept Iteface to tue, the followig optios ae available: PCIe0 CII REQ to ACK Latecy Timeout value 1-256 100 Eables CII REQ to ACK Latecy Timeout value (i clock cycles).
Eable Cofiguatio Itecept Iteface Moito
  • Tue
  • False
False Eables the cofiguatio itecept iteface moito.
Eable PCIe0/PCIe1 Vitio PCI CFG Iteface
  • Tue
  • False
False Eables the PCIe0/PCIe1 Vitio PCI CFG Iteface. Host ead ad wite accesses to VIRTIO PCI Cofig Access Data egiste uses this iteface fo its alteate access fuctioality.
Eable PCIe0/PCIe1 Eo Iteface
  • Tue
  • False
False Eable the Eo Iteface

AXI Itefaces 0/AXI Iteface 1 Settigs

Table 29.   GTS AXI Steamig IP Paametes: AXI Itefaces 0/AXI Iteface 1 Settigs Tab
Paamete Value Default Settig Desciptio

AXI-Lite Clock Fequecy (i MHz)

100–250 250

Select the GTS AXI Steamig IP AXI-Lite opeatig clock fequecy.

Refe to the Clock Domais i GTS AXI Steamig IP table fo moe ifomatio about the p0_axi_lite_clk fequecy.

PCIe0/PCIe1 Settigs

PCIe0/PCIe1 Base Addess Registes

Figue 35. Example PCIe* 0/ PCIe* 1 Base Addess Registes Tab i the GTS AXI Steamig IP Paamete Edito
Table 30.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 Base Addess Registes Tab
Paamete Value Paamete Desciptio
PCIe* 0/ PCIe* 1 Base Addess Registes
PCIe* 0/ PCIe* 1 PF<>/VF BAR Cofiguatio
BAR0 type
  • Disabled
  • 64-bit pefetchable memoy
  • 64-bit o-pefetchable memoy
  • 32-bit o-pefetchable memoy

If you select 64-bit pefetchable memoy, 2 cotiguous based addess egistes (BARs) ae combied to fom a 64-bit pefetchable BAR; you must set the highe umbeed BAR to Disabled.

Defiig memoy as pefetchable allows cotiguous data to be fetched ahead. Pefetchig memoy is advatageous whe the equeste may equie moe data fom the same egio tha was oigially equested. If you specify that a memoy is pefetchable, it must have the followig two attibutes:
  • Reads do ot have side effects such as chagig the value of the data ead.
  • Wite megig is allowed.
BAR1 type
  • Disabled
  • 32-bit o-pefetchable memoy

Fo a defiitio of pefetchable memoy, efe to the BAR0 type desciptio.

BAR2 type
  • Disabled
  • 64-bit pefetchable memoy
  • 64-bit o-pefetchable memoy
  • 32-bit o-pefetchable memoy

Fo a defiitio of pefetchable memoy ad a desciptio of what happes whe you select the 64-bit pefetchable memoy optio, efe to the BAR0 type desciptio.

BAR3 type
  • Disabled
  • 32-bit o-pefetchable memoy

Fo a defiitio of pefetchable memoy, efe to the BAR0 type desciptio.

BAR4 type
  • Disabled
  • 64-bit pefetchable memoy
  • 64-bit o-pefetchable memoy
  • 32-bit o-pefetchable memoy

Fo a defiitio of pefetchable memoy ad a desciptio of what happes whe you select the 64-bit pefetchable memoy optio, efe to the BAR0 type desciptio.

BAR5 type
  • Disabled
  • 32-bit o-pefetchable memoy

Fo a defiitio of pefetchable memoy, efe to the BAR0 type desciptio.

Expasio ROM Size
  • Disabled
  • 4 KBytes - 12 bits
  • 8 KBytes - 13 bits
  • 16 KBytes - 14 bits
  • 32 KBytes - 15 bits
  • 64 KBytes - 16 bits
  • 128 KBytes - 17 bits
  • 256 KBytes - 18 bits
  • 512 KBytes - 19 bits
  • 1 MBytes - 20 bits
  • 2 Bytes - 21 bits
  • 4 MBytes - 22 bits
  • 8 MBytes - 23 bits
  • 16 MBytes - 24 bits
Specifies a expasio ROM fom 4 KBytes to 16 MBytes whe eabled.
Note: This paamete is ot applicable fo Vitual Fuctio (VF).
BAR<> size

(whee = 0, 1, 2, 3, 4, o 5)

4 KBytes - 4 GBytes (32-bit BAR Type)

4 KBytes - 16 Ebytes(64-bit BAR Type)

Sets fom 12–64 bits pe base addess egiste (BAR). Specifies the size of the addess space accessible to BAR<> whe BAR<> is eabled.

PCIe0/PCIe1 Device Idetificatio Registes

Figue 36. Example PCIe* 0/ PCIe* 1 Device Idetificatio Registes Tab i the GTS AXI Steamig IP Paamete Edito
Table 31.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 Device Idetificatio Registes Tab
Paamete Value Paamete Desciptio
PCIe* 0/ PCIe* 1 PF<>/VF IDs
Vedo ID 0x00001172 Sets the ead-oly value of the Vedo ID egiste.
Device ID 0x00000000 Sets the ead-oly value of the Device ID egiste.
Revisio ID 0x00000001 Sets the ead-oly value of the Revisio ID egiste.
Class code 0x00ff0000 Sets the ead-oly value of the Class code egiste.
Subsystem Vedo ID 0x00000000 Sets the ead-oly value of the Subsystem Vedo ID egiste.
Subsystem Device ID 0x00000000 Sets the ead-oly value of the Subsystem Device ID egiste.
PCIe* 0/ PCIe* 1 VF IDs
Device ID 0x00000000 Sets the ead-oly value of the Device ID egiste fo the vitual fuctios.
Subsystem ID 0x00000000 Sets the ead-oly value of the Subsystem ID egiste fo the vitual fuctios.

PCIe0/PCIe1 PCI Expess / PCI Capabilities

Figue 37. Example PCIe* 0/ PCIe* 1 PCI Expess* / PCI Capabilities Tab i the GTS AXI Steamig IP Paamete Edito

PCIe0/PCIe1 Device
Table 32.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 Device Tab
Paamete Value Default Settig Desciptio
Maximum payload size suppoted
  • 128 Bytes
  • 256 Bytes
  • 512 Bytes
512 Bytes

Sets the ead-oly value of the max payload size of the Device Capabilities egiste ad optimizes fo this payload size.
Fuctio level eset
  • Tue
  • False
False Eables fuctio level eset. This optio is available whe Eable multiple physical fuctios is eabled. It is eabled by default whe Eable SR-IOV suppot is eabled.
Eable multiple physical fuctios
  • Tue
  • False
False

Eables multiple physical fuctios.
Whe you set Eable multiple physical fuctios to Tue, the followig optio is available:

Total physical fuctios (PFs)

1–4 1

Sets the umbe of physical fuctios (PFs). The IP ca suppot 1–4 PFs.
Eable SR-IOV suppot
  • Tue
  • False
False

Eables the SR-IOV suppot.
Whe you set Eable SR-IOV suppot to Tue, the followig optio is available:

Total vitual fuctios of physical fuctio 0 (PF0 VFs)

0–256

Note: 256 is the total vitual fuctios shaed amog the physical fuctios.
0

Sets the umbe of vitual fuctios (VFs) to be assiged to the physical fuctios (PFs).

Example of maximum VFs of the PFs:

If PF0 ad PF1 is eabled with PF0 VFs set to 200.

Maximum PF1 VFs = 256 - 200 = 56.
Whe you set Eable SR-IOV suppot to Tue ad povide a Total physical fuctios (PFs) value geate tha 1, the followig optio is available:

Total vitual fuctios of physical fuctio 1 (PF1 VFs)

0
Whe you set Eable SR-IOV suppot to Tue ad povide a Total physical fuctios (PFs) value geate tha 2, the followig optio is available:

Total vitual fuctios of physical fuctio 2 (PF2 VFs)

0
Whe you set Eable SR-IOV suppot to Tue ad povide a Total physical fuctios (PFs) value geate tha 3, the followig optio is available:

Total vitual fuctios of physical fuctio 3 (PF3 VFs)

0
PCIe0/PCIe1 Lik
Note: This tab is visible i the Paamete Edito oly if the PCIe0/PCIe1 Pot Mode paamete i the System Settigs tab is set to Root Pot.
Table 33.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 Lik Tab
Paamete Value Default Settig Desciptio
Lik pot umbe (Root Pot oly) 0 - 255 1 Sets the ead-oly value of the pot umbe field i the Lik Capabilities egiste. This paamete is fo the Root Pots oly.
Slot clock cofiguatio
  • Tue
  • False
Tue

Whe this paamete is Tue, it idicates that the Edpoit uses the same physical efeece clock that the system povides o the coecto. Whe it is False, the IP coe uses a idepedet clock egadless of the pesece of a efeece clock o the coecto. This paamete sets the Slot Clock Cofiguatio bit (bit-12) i the PCI Expess* Lik Status egiste.

PCIe0/PCIe1 Slot
Note: This tab is visible i the Paamete Edito oly if the PCIe0/PCIe1 Pot Mode paamete i the System Settigs tab is set to Root Pot.
Table 34.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 Slot Tab
Paamete Value Default Settig Desciptio
Use Slot Powe egistes (Root Pot oly)
  • Tue
  • False
False This paamete is oly suppoted i Root Pot mode. The slot capability is equied fo Root Pots if a slot is implemeted o the pot. Slot status is ecoded i the PCI Expess* Capabilities egiste.
Slot powe scale 0 - 3 0 Specifies the scale used fo the slot powe limit. The followig coefficiets ae defied:
  • 0 = 1.0x
  • 1 = 0.1x
  • 2 = 0.01x
  • 3 = 0.001x
The default value pio to hadwae ad fimwae iitializatio is b’00. Wites to this egiste also cause the pot to sed the Set_Slot_Powe_Limit message.
Slot powe limit 0 - 255 0 I combiatio with the Slot powe scale value, specifies the uppe limit i watts fo the powe supplied by the slot.
Slot umbe 0 - 8191 0 Specifies the slot umbe.
PCIe0/PCIe1 Legacy Iteupt Pi Registe
Table 35.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 Legacy Iteupt Pi Registe Tab
Paamete Value Default Settig Desciptio
Set Iteupt Pi fo PF<>

(whee = 0, 1, 2, 3 )
  • INTA
  • INTB
  • INTC
  • INTD
  • NO INT
NO INT

Sets Iteupt Pi fo PF0.

  • Whe you do ot wat to use Legacy Iteupts, set the optio to NO INT.
  • Whe you wat to use Legacy Iteupts ad disable Eable multiple physical fuctios, the oly optio available is INTA.
  • Whe you set Eable multiple physical fuctios to Tue, the available optios ae INTA INTB, INTC, ad INTD.
PCIe0/PCIe1 PTM
Table 36.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 PTM Tab
Paamete Value Default Settig Desciptio
Eable PTM
  • Tue
  • False
False

Whe selected, Pecisio Time Measuemet (PTM) Capability is added.
Whe you set Eable PTM to Tue, the followig optio is available:

Peiod betwee each automatic update of PTM cotext (i ms)

  • Disable
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
Disable

Detemies the PTM cotext auto-update iteval.

Selectig Disable pevets PTM cotext auto-update.

PCIe0/PCIe1 LTR
Table 37.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 LTR Tab
Paamete Value Default Settig Desciptio
PCIe0/PCIe1 eable LTR
  • Tue
  • False
False Eables Latecy Toleace Repotig (LTR). This is a ew mechaism that eables Edpoits to sed ifomatio about thei latecy equiemets fo memoy ead/wites ad iteupts fo PCIe* 0/ PCIe* 1.
PCIe0/PCIe1 MSI
Table 38.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 MSI Tab
Paamete Value Default Settig Desciptio
PF<> Eable MSI

(whee = 0, 1, 2, 3 )
  • Tue
  • False
False Eables MSI fuctioality fo PF. If you tu o this paamete, the PF Numbe of MSI messages equested paamete appeas, which allows you to set the umbe of MSI messages.
If you set PF Eable MSI to Tue, the followig optios ae available: PF MSI Exteded Data Capable
  • Tue
  • False
False Eables o disables the MSI exteded data capability fo PF.
PF MSI 64-bit addessig
  • Tue
  • False
False Eables o disables the MSI 64-bit addessig fo PF.
PF Numbe of MSI messages equested
  • 1
  • 2
  • 4
  • 8
  • 16
  • 32
1 Sets the umbe of messages that the applicatio ca equest i the multiple message capable field of the Message Cotol egiste.
PCIe0/PCIe1 MSI-X
Table 39.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 PF/VF MSI-X Tabs
Paamete Value Default Settig Desciptio
Eable MSI-X/Eable VF MSI-X
  • Tue
  • False
False Eables o disables the MSI-X fuctioality.
Table size

0x0–0x7FF

(oly values of powes of two mius 1 ae valid)

 0

Sets the umbe of eties i the MSI-X table. The system softwae eads this field to detemie the MSI-X table size <>, which is ecoded as <-1>. Fo example, a etued value of 2047 idicates a table size of 2048.

This field is ead-oly.

Addess offset: 0x068[26:16].
Table offset 0x0–0x1FFFFFFF 0x00000000

Poits to the base of the MSI-X table. The lowe 3 bits of the table BAR idicato (BIR) ae set to zeo by softwae to fom a 64-bit qwod-aliged offset

This field is ead-oly afte beig pogammed.
Table BAR idicato 0x0–0x5 0

Specifies which oe of a fuctio's BARs, located begiig at 0x10 i the Cofiguatio Space, is used to map the MSI-X table ito memoy space.

This field is ead-oly afte beig pogammed.
PBA BAR idicato 0x0–0x5 0

Specifies the fuctio's Base Addess egiste, located begiig at 0x10 i the Cofiguatio Space, that maps the MSI-X PBA ito memoy space.

This field is ead-oly afte beig pogammed.
Pedig bit aay (PBA) offset 0x0–0x1FFFFFFF 0x00000000

Used as a offset fom the addess cotaied i oe of the fuctio's Base Addess egistes to poit to the base of the MSI-X PBA.

The lowe 3 bits of the PBA BIR ae set to zeo by softwae to fom a 32-bit qwod-aliged offset.

This field is ead-oly afte beig pogammed.
VF Table size

0x0–0x7FF

(oly values of powes of two mius 1 ae valid)

 0
Sets the umbe of eties i the MSI-X table fo VFs. MSI-X caot be disabled fo VFs. Set to 1 to save esouces.
Note: This paamete is oly available fo PF.
PCIe0/PCIe1 PASID
Table 40.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 PASID Tab
Paamete Value Default Settig Desciptio
PCIe* 0/ PCIe* 1 PF eable PASID

(whee = 0, 1, 2, 3 )
  • Tue
  • False
False Eables the PASID (Pocess Addess Space ID) Optioal featue, which allows a sigle edpoit to be shaed by multiple pocesses by povided each a vitual 64-bit addess space PCIe* 0/ PCIe* 1 PF.
Whe you set PCIe* 0/ PCIe* 1 PF eable PASID to Tue, the followig optios ae available: PCIe* 0 PF Eable Execute Pemissio Suppot
  • Tue
  • False
False Eables o disables the PASID Execute Pemissio Suppot fo PCIe* 0/ PCIe* 1 PF.
PCIe* 0 PF max PASID width 0–20 0 Sets the maximum PASID width fo PCIe* 0/ PCIe* 1 PF.
PCIe* 0 PF eable Pivileged Mode Suppot
  • Tue
  • False
False Eables o disables the PASID Pivileged Mode Suppot fo PCIe* 0/ PCIe* 1 PF.
PCIe0/PCIe1 DEV SER
Table 41.   GTS AXI Steamig IP Paametes: PCIe* 0/ PCIe* 1 DEV SER Tab
Paamete Value Default Settig Desciptio
Eable Device Seial Numbe Capability
  • Tue
  • False
False Eables Device Seial Numbe Capability (DEVSER) optioal exteded capability is 64-bit that is uique fo ay give PCIe* device.
Device Seial Numbe (DW1) 32-bit value 0x0000_0000_0000_0000 Sets the lowe 32 bits of IEEE 64 bit Device Seial Numbe (DW1).
Device Seial Numbe (DW2) 32-bit value 0x0000_0000_0000_0000 Sets the uppe 32 bits of IEEE 64 bit Device Seial Numbe (DW2).
PCIe0/PCIe1 PRS
Table 42.   GTS AXI Steamig IP Paametes: PRS Tab
Paamete Value Default Settig Desciptio
PF<> eable PRS

(whee = 0, 1, 2, 3)

  • Tue
  • False
False Eable o disable Page Request Sevice (PRS) capability.
PF<> Page Request Sevices Outstadig Capacity

(whee = 0, 1, 2, 3)

0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0000_0000_0000 This is the uppe limit o the umbe of pages that ca be usefully allocated to the Page Request Iteface.
PCIe0/PCIe1 Powe Maagemet
Table 43.   GTS AXI Steamig IP Paametes: Powe Maagemet Tab
Paamete Value Default Settig Desciptio
Edpoit L0s acceptable latecy
  • Maximum of 64 s
  • Maximum of 128 s
  • Maximum of 256 s
  • Maximum of 512 s
  • Maximum of 1 μs
  • Maximum of 2 μs
  • Maximum of 4 μs
  • No limit
Maximum of 64 s Sets the ead-oly value of the edpoit L0s acceptable latecy field of the Device Capabilities egiste. This value should be based o the latecy that the applicatio laye ca toleate fo ay lik betwee the device ad the Root complex to exit the L0s state. This settig is disabled fo oot pots.
Edpoit L1 acceptable latecy
  • Maximum of 1 μs
  • Maximum of 2 μs
  • Maximum of 4 μs
  • Maximum of 8 μs
  • Maximum of 16 μs
  • Maximum of 32 μs
  • Maximum of 64 μs
  • No limit
Maximum of 1 μs Sets the acceptable latecy that a edpoit ca withstad i the tasitio fom the L1 to L0 state. It is a idiect measue of the edpoit iteal buffeig. This settig is disabled fo oot pots.
PCIe0/PCIe1 VSEC
Table 44.   GTS AXI Steamig IP Paametes: VSEC Tab
Paamete Value Default Settig Desciptio
Vedo Specific Exteded Capability N/A False Eables Vedo Specific Exteded Capability (VSEC). This paamete seves as a idicato of status of the VSEC eablemet i the IP. The value of this paamete become tue whe you eable the Cofiguatio Extesio Bus Iteface ad specify the ext addess poites i the Itefaces tab.
PF<> Vedo Specific Exteded Capability Offset

(whee = 0, 1, 2, 3 )

N/A 0x00000000 Sets the ead-oly base addess of the 12-bit Vedo Specific Exteded Capability offset fo PF<>. This paamete seve as a idicato of ext addess poite value i byte-addessig fomat of the VSEC exteded capability. The value of this paamete is show whe you eable the Cofiguatio Extesio Bus Iteface ad specify the ext addess poites i the Itefaces tab.
Use ID egiste fom the Vedo Specific Exteded Capability 0x00000000 - 0x0000ffff 0x00000000 Sets the ead-oly value of the 16-bit Use ID egiste fom the Vedo Specific Exteded Capability.
Dops Vedo Type0 Messages
  • Tue
  • False
False Whe selected, eceived Vedo MSG Type0 is dopped as a Usuppoted Request (UR). Othewise, eceived Vedo MSG Type0 is ot dopped, but visible o AXI4-Steam Receive iteface. This optio is ot applicable fo TLP Bypass mode. I TLP Bypass mode, eceived Vedo MSG Type0 is always visible o AXI4-Steam Receive iteface.
Dops Vedo Type1 Messages
  • Tue
  • False
False Whe selected, eceived Vedo MSG Type1 ae dopped siletly. Othewise, eceived Vedo MSG Type1 ae ot dopped, but visible o AXI4-Steam Receive iteface. This optio is ot applicable fo TLP Bypass mode. I TLP Bypass mode, eceived Vedo MSG Type1 ae always visible o AXI4-Steam Receive iteface.
PCIe0/PCIe1 ATS
Table 45.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 ATS Tab
Paamete Value Default Settig Desciptio
Eable Addess Taslatio Sevices (ATS)
  • Tue
  • False
False Whe you eable the Addess Taslatio Sevices (ATS), sedes ca equest ad cache taslated addesses usig the RP memoy space fo late use.
PCIe0/PCIe1 TPH
Table 46.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 TPH Tab
Paamete Value Default Settig Desciptio
Eable TLP Pocessig Hits (TPH)
  • Tue
  • False
False Whe you eable the TLP Pocessig Hits (TPH), it may impove latecy ad taffic cogestio.
PCIe0/PCIe1 ACS
Note: To eable ACS capabilities, you must fist eable suppot fo multiple physical fuctios.
Table 47.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 ACS Tab
Paamete Value Default Settig Desciptio
Eable Access Cotol Sevice (ACS)
  • Tue
  • False
False ACS defies a set of cotol poits withi a PCI Expess* topology to detemie whethe a TLP is to be outed omally, blocked, o ediected.
Eable ACS P2P Taffic Suppot
  • Tue
  • False
False Idicates if the IP suppots pee to pee taffic.

This paamete is visible oly if Eable Access Cotol Sevice (ACS) is set to Tue.

Eable ACS P2P Egess Cotol
  • Tue
  • False
False

Idicates if the compoet implemets ACS P2P Egess Cotol.

This paamete is visible oly if Eable ACS P2P Taffic Suppot is set to Tue.

Eable ACS P2P Egess Cotol vecto size 0 - 255 8 Idicates the umbe of bits i the ACS P2P Egess Cotol Vecto. This paamete is visible oly if Eable ACS P2P Egess Cotol is set to Tue.
PCIe0/PCIe1 Hot-Plug
Table 48.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 Hot-Plug Tab
Paamete Value Default Settig Desciptio
Eable Hot Plug
  • Tue
  • False
False Eable o disable Hot-Plug capability. This paamete is fo the Root Pots oly.
PCIe0/PCIe1 VIRTIO
Table 49.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 VIRTIO Tab
Paamete Value Default Settig Desciptio
Eable VIRTIO suppot
  • Tue
  • False
False To eable VIRTIO Capabilities fo PFs ad VFs.
PCIe0/PCIe1 PF<> VIRTIO STRUCTURES
Note: These paametes ae oly available whe you eable the Eable VIRTIO suppot paamete settig.
Table 50.   GTS AXI Steamig IP Paametes: PCIe0/PCIe1 PF0 VIRTIO STRUCTURES Tab
Paamete Value Default Settig Desciptio
Eable VIRTIO Capabilities fo PF<>/PF<> VFs

(whee = 0, 1, 2, 3 )

  • Tue
  • False
False Eables VIRTIO Capabilities fo VIRTIO Capable Devices.
Eable Device Specific Capability fo PF<>/PF<> VFs

(whee = 0, 1, 2, 3 )

  • Tue
  • False
False Eables Device Specific Capability fo VIRTIO Device o PF0.

PCIe0/PCIe1 PF/VF Commo Cofiguatio Stuctue

Note: These paametes ae oly available whe you eable the Eable VIRTIO Capabilities fo PF<>/PF<> VFs paamete settig.
Table 51.   GTS AXI Steamig IP Paametes: PF/VF Commo Cofiguatio Stuctue Tab
Paamete Value Default Settig Desciptio
BAR idicato 0-5 0 Idicates the BAR holdig the Commo Cofiguatio Stuctue.
Offset withi BAR 0-0x1fff_ffff 0 Idicates the statig positio of Commo Cofiguatio Stuctue i a give BAR.
Stuctue legth i Bytes 0-0x1fff_ffff 0 Idicates the legth i bytes of Commo Cofiguatio Stuctue.

PCIe0/PCIe1 PF/VF Notificatio Stuctue

Note: These paametes ae oly available whe you eable the Eable VIRTIO Capabilities fo PF<>/PF<> VFs paamete settig.
Table 52.   GTS AXI Steamig IP Paametes: PF/VF Notificatio Stuctue Tab
Paamete Value Default Settig Desciptio
BAR idicato 0-5 0 Idicates the BAR holdig the Notificatio Stuctue.
Offset withi BAR 0-0x1fff_ffff 0 Idicates the statig positio of Notificatio Stuctue i a give BAR.
Stuctue legth i Bytes 0-0x1fff_ffff 0 Idicates the legth i bytes of Notificatio Stuctue.
Notify Off Multiplie 0-0x1fff_ffff 0 Idicates the multiplie fo queue_otify_off.

PCIe0/PCIe1 PF/VF ISR Status Stuctue

Table 53.   GTS AXI Steamig IP Paametes: PF/VF ISR Status Stuctue Tab
Paamete Value Default Settig Desciptio
BAR idicato 0-5 0 Idicates the BAR holdig the ISR Status Stuctue.
Offset withi BAR 0-0x1fff_ffff 0 Idicates the statig positio of ISR Status Stuctue i a give BAR.
Stuctue legth i Bytes 0-0x1fff_ffff 0 Idicates the legth i bytes of ISR Status Stuctue.

PCIe0/PCIe1 PF/VF Device Specific Stuctue

Table 54.   GTS AXI Steamig IP Paametes: PF/VF Device Specific Stuctue Tab
Paamete Value Default Settig Desciptio
BAR idicato 0-5 0 Idicates the BAR holdig the Device Specific Stuctue.
Offset withi BAR 0-0x1fff_ffff 0 Idicates the statig positio of Device Specific Stuctue i a give BAR.
Stuctue legth i Bytes 0-0x1fff_ffff 0 Idicates the legth i bytes of Device Specific Stuctue.

Diagostics

Figue 38. Example Diagostics Tab i the GTS AXI Steamig IP Paamete Edito
Table 55.   GTS AXI Steamig IP Paametes: Diagostics Tab
Paamete Value Default Settig Desciptio
Eable HIP Iteface Adapto Debug Moito
  • Tue
  • False
False Eables the HIP Iteface Adapto Debug Moito. Refe to Debug Registes fo moe ifomatio..
Eable HIP Iteface Adapto Pefomace Moito
  • Tue
  • False
False Eables the HIP Iteface Adapto Pefomace Moito. Refe to Pefomace Moito Registes fo moe ifomatio.
Eable Debug Toolkit
  • Tue
  • False
False Eables the debug toolkit fo the GTS AXI Steamig IP.
Level Two Title